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PDF 7FLITE05 Data sheet ( Hoja de datos )

Número de pieza 7FLITE05
Descripción ST7FLITE05
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



Total 30 Páginas
		
7FLITE05 Hoja de datos, Descripción, Manual
ST7LITE0, ST7SUPERLITE
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
DATA EEPROM, ADC, TIMERS, SPI
s Memories
– 1K or 1.5K bytes single voltage Flash Pro-
gram memory with read-out protection, In-Cir-
cuit and In-Application Programming (ICP and
IAP). 10K write/erase cycles guaranteed, data
retention: 20 years at 55°C.
– 128 bytes RAM.
– 128 bytes data EEPROM with read-out pro-
tection. 300K write/erase cycles guaranteed,
data retention: 20 years at 55°C.
s Clock, Reset and Supply Management
– 3-level low voltage supervisor (LVD) and aux-
iliary voltage detector (AVD) for safe power-
on/off procedures
– Clock sources: internal 1MHz RC 1% oscilla-
tor or external clock
– PLL x4 or x8 for 4 or 8 MHz internal clock
– Four Power Saving Modes: Halt, Active-Halt,
Wait and Slow
s Interrupt Management
– 10 interrupt vectors plus TRAP and RESET
– 4 external interrupt lines (on 4 vectors)
s I/O Ports
– 13 multifunctional bidirectional I/O lines
– 9 alternate function lines
– 6 high sink outputs
s 2 Timers
– One 8-bit Lite Timer (LT) with prescaler in-
cluding: watchdog, 1 realtime base and 1 in-
put capture.
DIP16
SO16
150”
– One 12-bit Auto-reload Timer (AT) with output
compare function and PWM
s 1 Communication Interface
– SPI synchronous serial interface
s A/D Converter
– 8-bit resolution for 0 to VDD
– Fixed gain Op-amp for 11-bit resolution in 0 to
250 mV range (@ 5V VDD)
– 5 input channels
s Instruction Set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
s Development Tools
– Full hardware/software development package
Device Summary
Features
ST7SUPERLITE
ST7LITES2
ST7LITES5
ST7LITE02
ST7LITE0
ST7LITE05
ST7LITE09
Program memory - bytes
RAM (stack) - bytes
Data EEPROM - bytes
Peripherals
Operating Supply
CPU Frequency
Operating Temperature
Packages
1K
128 (64)
-
LT Timer w/ Wdg,
AT Timer w/ 1 PWM,
SPI
1K 1.5K
128 (64)
128 (64)
--
LT Timer w/ Wdg, LT Timer w/ Wdg,
AT Timer w/ 1 PWM, AT Timer w/ 1 PWM,
SPI, 8-bit ADC
SPI
2.4V to 5.5V
1MHz RC 1% + PLLx4/8MHz
-40°C to +85°C
SO16 150”, DIP16
1.5K
1.5K
128 (64)
128 (64)
- 128
LT Timer w/ Wdg,
AT Timer w/ 1 PWM, SPI,
8-bit ADC w/ Op-Amp
August 2003
Rev. 2.4
1/122
1

1 page

7FLITE05 pdf
ST7LITE0, ST7SUPERLITE
1 INTRODUCTION
The ST7LITE0 and ST7SUPERLITE are members
of the ST7 microcontroller family. All ST7 devices
are based on a common industry-standard 8-bit
core, featuring an enhanced instruction set.
The ST7LITE0 and ST7SUPERLITE feature
FLASH memory with byte-by-byte In-Circuit Pro-
gramming (ICP) and In-Application Programming
(IAP) capability.
Under software control, the ST7LITE0 and
ST7SUPERLITE devices can be placed in WAIT,
SLOW, or HALT mode, reducing power consump-
tion when the application is in idle or standby state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
For easy reference, all parametric data are located
in section 13 on page 78.
Figure 1. General Block Diagram
VDD
VSS
RESET
1 MHz. RC OSC
+
PLL x 4 or x 8
Internal
CLOCK
LVD/AVD
POWER
SUPPLY
CONTROL
8-BIT CORE
ALU
FLASH
MEMORY
(1 or 1.5K Bytes)
RAM
(128 Bytes)
DATA EEPROM
(128 Bytes)
LITE TIMER
w/ WATCHDOG
PORT A
12-BIT AUTO-
RELOAD TIMER
SPI
PORT B
8-BIT ADC
PA7:0
(8 bits)
PB4:0
(5 bits)
5/122
1

5 Page

7FLITE05 arduino
ST7LITE0, ST7SUPERLITE
Address
003Ah
003Bh to
007Fh
Block
SI
Register
Label
Register Name
SICSR
System Integrity Control/Status Register
Reserved area (45 bytes)
Reset
Status
0xh
Remarks
R/W
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
11/122
1

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