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Número de pieza | WM8958 | |
Descripción | Multi-Channel Audio Hub CODEC | |
Fabricantes | Wolfson Microelectronics | |
Logotipo | ||
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WM8958
Multi-Channel Audio Hub CODEC for Smartphones
DESCRIPTION
FEATURES
The WM8958[1] is a highly integrated ultra-low power hi-fi
CODEC designed for smartphones and other portable devices
rich in multimedia features.
An integrated stereo class D/AB speaker driver and class W
headphone driver minimize power consumption during audio
playback.
The device requires only two voltage supplies, with all other
internal supply rails generated from integrated LDOs.
Stereo full duplex asynchronous sample rate conversion and
multi-channel digital mixing combined with powerful analogue
mixing allow the device to support a huge range of different
architectures and use cases.
A multiband compressor and programmable parametric EQ
provide volume maximisation and speaker compensation in the
digital playback paths. The dynamic range controller can be
used in record or playback paths for maintaining a constant
signal level, maximizing loudness and protecting speakers
against overloading and clipping.
A smart digital microphone interface provides power regulation,
a low jitter clock output and decimation filters for up to four
digital microphones. Microphone activity detection with interrupt
is available. Impedance sensing and measurement is provided
for external accessory / push-button detection.
Fully differential internal architecture and on-chip RF noise filters
ensure a very high degree of noise immunity. Active ground loop
noise rejection and DC offset correction help prevent pop noise
and suppress ground noise on the headphone outputs.
24-bit 4-channel hi-fi DAC and 2-channel hi-fi ADC
100dB SNR during DAC playback (‘A’ weighted)
Smart MIC interface
- Power, clocking and data input for up to four digital MICs
- High performance analogue MIC interface
- MIC activity detect & interrupt allows processor to sleep
- Impedance sensing for accessory / push-button detection
2W stereo (2 x 2W) class D/AB speaker driver
Capless Class W headphone drivers
- Integrated charge pump
- 5.3mW total power for DAC playback to headphones
4 Line outputs (single-ended or differential)
BTL Earpiece driver
Digital audio interfaces for multi-processor architecture
- Asynchronous stereo duplex sample rate conversion
- Powerful mixing and digital loopback functions
ReTuneTM Mobile 5-band, 6-channel parametric EQ
Multiband compressor and dynamic range controller
Dual FLL provides all necessary clocks
- Self-clocking modes allow processor to sleep
- All standard sample rates from 8kHz to 96kHz
Active noise reduction circuits
- DC offset correction removes pops and clicks
- Ground loop noise cancellation
Integrated LDO regulators
72-ball W-CSP package (4.516 x 4.258 x 0.698mm)
APPLICATIONS
Smartphones and music phones
Portable navigation
Tablets
eBooks
Portable Media Players
WOLFSON MICROELECTRONICS plc
Pre-Production, August 2012, Rev 3.4
[1] This product is protected by Patents US 7,622,984, US 7,626,445,US 7,765,019 and GB 2,432,765
Copyright 2012 Wolfson Microelectronics plc
1 page Pre-Production
WM8958
CLOCKING AND SAMPLE RATES.............................................................................. 200
AIF1CLK ENABLE ......................................................................................................................................................... 201
AIF1 CLOCKING CONFIGURATION ............................................................................................................................ 202
AIF2CLK ENABLE ......................................................................................................................................................... 204
AIF2 CLOCKING CONFIGURATION ............................................................................................................................ 204
MISCELLANEOUS CLOCK CONTROLS ...................................................................................................................... 206
BCLK AND LRCLK CONTROL...................................................................................................................................... 209
CONTROL INTERFACE CLOCKING ............................................................................................................................ 211
FREQUENCY LOCKED LOOP (FLL) ............................................................................................................................ 211
FREE-RUNNING FLL CLOCK....................................................................................................................................... 217
GPIO OUTPUTS FROM FLL ......................................................................................................................................... 218
EXAMPLE FLL CALCULATION..................................................................................................................................... 219
EXAMPLE FLL SETTINGS............................................................................................................................................ 220
SAMPLE RATE CONVERSION ................................................................................... 221
SAMPLE RATE CONVERTER 1 (SRC1) ...................................................................................................................... 221
SAMPLE RATE CONVERTER 2 (SRC2) ...................................................................................................................... 221
SAMPLE RATE CONVERTER RESTRICTIONS .......................................................................................................... 221
SAMPLE RATE CONVERTER CONFIGURATION ERROR INDICATION ................................................................... 222
CONTROL INTERFACE............................................................................................... 224
CONTROL WRITE SEQUENCER................................................................................ 227
INITIATING A SEQUENCE............................................................................................................................................ 227
PROGRAMMING A SEQUENCE .................................................................................................................................. 228
DEFAULT SEQUENCES ............................................................................................................................................... 230
POP SUPPRESSION CONTROL ................................................................................ 237
DISABLED LINE OUTPUT CONTROL.......................................................................................................................... 237
LINE OUTPUT DISCHARGE CONTROL ...................................................................................................................... 238
VMID REFERENCE DISCHARGE CONTROL.............................................................................................................. 238
INPUT VMID CLAMPS .................................................................................................................................................. 238
LDO REGULATORS .................................................................................................... 239
REFERENCE VOLTAGES AND MASTER BIAS ......................................................... 241
POWER MANAGEMENT ............................................................................................. 243
THERMAL SHUTDOWN .............................................................................................. 248
POWER ON RESET..................................................................................................... 249
QUICK START-UP AND SHUTDOWN ........................................................................ 251
SOFTWARE RESET AND DEVICE ID......................................................................... 252
REGISTER MAP ................................................................................................ 253
REGISTER BITS BY ADDRESS .................................................................................. 265
APPLICATIONS INFORMATION ...................................................................... 360
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 360
AUDIO INPUT PATHS................................................................................................................................................... 360
HEADPHONE OUTPUT PATH...................................................................................................................................... 361
EARPIECE DRIVER OUTPUT PATH............................................................................................................................ 362
LINE OUTPUT PATHS .................................................................................................................................................. 362
POWER SUPPLY DECOUPLING ................................................................................................................................. 363
CHARGE PUMP COMPONENTS ................................................................................................................................. 364
MICROPHONE BIAS CIRCUIT ..................................................................................................................................... 364
EXTERNAL ACCESSORY DETECTION COMPONENTS ............................................................................................ 366
CLASS D SPEAKER CONNECTIONS .......................................................................................................................... 367
RECOMMENDED EXTERNAL COMPONENTS DIAGRAM ......................................................................................... 368
DIGITAL AUDIO INTERFACE CLOCKING CONFIGURATIONS................................. 370
PCB LAYOUT CONSIDERATIONS ............................................................................. 373
CLASS D LOUDSPEAKER CONNECTION .................................................................................................................. 373
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PP, August 2012, Rev 3.4
5
5 Page Pre-Production
WM8958
The following table identifies the power domain and ground reference associated with each of the input / output pins.
PIN NO
F1
F4
D3
F2
G3
G1
E4
D6
H1
H3
G4
H4
F5
E5
H6
F6
F9
F8
C7
C8
B7
C6
B9
NAME
ADCDAT1
ADCDAT2
ADDR
BCLK1
BCLK2
DACDAT1
DACDAT2
DMICCLK
GPIO1/ADCLRCLK1
GPIO6/ADCLRCLK2
GPIO8/DACDAT3
GPIO9/ADCDAT3
GPIO10/LRCLK3
GPIO11/BCLK3
HPOUT1L
HPOUT1R
HPOUT2N
HPOUT2P
IN1LN
IN1LP
IN1RN
IN1RP
IN2LN/DMICDAT1
B8 IN2LP/VRXN
A8 IN2RN/DMICDAT2
A9 IN2RP/VRXP
C3 LDO1ENA
D5 LDO2ENA
C5 LINEOUT1N
B5 LINEOUT1P
C4 LINEOUT2N
B4 LINEOUT2P
D4 LRCLK1
H2 LRCLK2
E1 MCLK1
D2 MCLK2
E9 MICDET
E3 SCLK
G2 SDA
A4 SPKMODE
B3 SPKOUTLN
A3 SPKOUTLP
B1 SPKOUTRN
B2 SPKOUTRP
POWER DOMAIN
DBVDD1
DBVDD2
DBVDD1
DBVDD1
DBVDD2
DBVDD1
DBVDD2
MICBIAS1
DBVDD1
DBVDD2
DBVDD3
DBVDD3
DBVDD3
DBVDD3
CPVOUTP, CPVOUTN
CPVOUTP, CPVOUTN
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1 (IN2LN) or
MICBIAS1 (DMICDAT1)
AVDD1
AVDD1 (IN2RN) or
MICBIAS1 (DMICDAT2)
AVDD1
DBVDD1
DBVDD1
AVDD1
AVDD1
AVDD1
AVDD1
DBVDD1
DBVDD2
DBVDD1
DBVDD1
MICBIAS2
DBVDD1
DBVDD1
DBVDD1
SPKVDD1
SPKVDD1
SPKVDD2
SPKVDD2
GROUND DOMAIN
DGND
DGND
DGND
DGND
DGND
DGND
DGND
AGND
DGND
DGND
DGND
DGND
DGND
DGND
CPGND
CPGND
HP2GND
HP2GND
AGND
AGND
AGND
AGND
AGND
AGND
AGND (IN2RN) or
DGND (DMICDAT2)
AGND
DGND
DGND
AGND
AGND
AGND
AGND
DGND
DGND
DGND
DGND
AGND
DGND
DGND
DGND
SPKGND1
SPKGND1
SPKGND2
SPKGND2
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PP, August 2012, Rev 3.4
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet WM8958.PDF ] |
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