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PDF NT5CC128M8FN-DI Data sheet ( Hoja de datos )

Número de pieza NT5CC128M8FN-DI
Descripción 1Gb SDRAM
Fabricantes Nanya 
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DDR3(L) 1Gb SDRAM
NT5CB(C)128M8FN / NT5CB(C)64M16FP
Nanya Technology Corp.
NT5CB(C)128M8FN / NT5CB(C)64M16FP
Commercial, Industrial and Automotive DDR3(L) 1Gb SDRAM
Features
JEDEC DDR3 Compliant
- 8n Prefetch Architecture
- Differential Clock(CK/) and Data Strobe(DQS/)
- Double-data rate on DQs, DQS and DM
Data Integrity
- Auto Self Refresh (ASR) by DRAM built-in TS
- Auto Refresh and Self Refresh Modes
Power Saving Mode
- Partial Array Self Refresh (PASR)1
- Power Down Mode
Signal Integrity
- Configurable DS for system compatibility
- Configurable On-Die Termination
- ZQ Calibration for DS/ODT impedance accuracy via
external ZQ pad (240 ohm ± 1%)
Signal Synchronization
- Write Leveling via MR settings 7
- Read Leveling via MPR
Interface and Power Supply
- SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V)
- SSTL_1354 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)
Speed Grade (CL-TRCD-TRP) 2,3
- 2133 Mbps / 14-14-14
- 1866 Mbps / 13-13-13
- 1600 Mbps / 10-10-10,11-11-11
Options
Temperature Range (Tc) 5
- Commercial Grade = 0~95
- Industrial Grade (-I) = -40~95
- Automotive Grade 2 (-H) = -40~105
- Automotive Grade 3 (-A) = -40~95
Programmable Functions
CAS Latency (5/6/7/8/9/10/11/12/13/14)
CAS Write Latency (5/6/7/8/9/10)
Additive Latency (0/CL-1/CL-2)
Write Recovery Time (5/6/7/8/10/12/14/16)
Burst Type (Sequential/Interleaved)
Burst Length (BL8/BC4/BC4 or 8 on the fly)
Self RefreshTemperature Range(Normal/Extended)
Output Driver Impedance (34/40)
On-Die Termination of Rtt_Nom(20/30/40/60/120)
On-Die Termination of Rtt_WR(60/120)
Precharge Power Down (slow/fast)
Packages / Density Information
Lead-free RoHS compliance and Halogen-free
1Gb
(Org. / Package)
Length x Width Ball pitch
(mm)
(mm)
128Mbx8
78-ball
TFBGA
8.00 x 10.50
0.80
64Mbx16
96-ball
TFBGA
9.00 x 13.00
0.80
Density and Addressing
Organization
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page Size
tREFI(us) 5
tRFC(ns) 6
128Mb x 8
64Mb x 16
BA0 BA2
BA0 BA2
A10 / AP
A12 / 
A10 / AP
A12 / 
A0 A13
A0 A9
A0 A12
A0 A9
1KB 2KB
Tc<=85:7.8, Tc>85:3.9
110ns
NOTE 1
NOTE 2
NOTE 3
NOTE 4
NOTE 5
NOTE 6
NOTE 7
Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand.
The timing specification of high speed bin is backward compatible with low speed bin.
Please refer to ordering information for the deailts (DDR3, DDR3L, DDR3L RS).
SSTL_135 compatible to SSTL_15. That means 1.35V DDR3L are backward compatible to 1.5V DDR3 parts. 1.35V DDR3L-RS parts are exceptional and
unallowable to be compatible to 1.35V DDR3L and 1.5V DDR3 parts.
If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9us interval refresh rate. Extended SRT or ASR must be enabled.
Violating tRFC specification will induce malfunction.
Only Support prime DQs feedback for each byte lane. Please contact with NTC for the feedback of all DQs which is enabled by using an electrical fuse.
Version 1.4
02/2014
1 Nanya Technology Cooperation ©
NTC has the rights to change any specifications or product without notification.
All Rights Reserved.

1 page




NT5CC128M8FN-DI pdf
DDR3(L) 1Gb SDRAM
NT5CB(C)128M8FN / NT5CB(C)64M16FP
NANYA Component Part Numbering Guide
NANYA
Technology
NT 5C B 128M8 F N
Product Family
5S = SDRAM
5D = DDR SDRAM
5T = DDR2 SDRAM
5C = DDR3 SDRAM
Interface & Power( VDD& VDDQ )
V = LVTTL (3.3V , 3.3V)
E = LVTTL (2.5V , 2.5V)
S = SSTL_2 (2.5V , 2.5V)
M = LVTTL (1.8V , 1.8V)
U = SSTL_ 18 (1.8V , 1.8V)
B = SSTL_ 15 (1.5V , 1.5V)
A = SSTL_ 18 (2.0V , 2.0V)
C = SSTL_135 (1.35V , 1.35V)
F = SSTL_125 (1.25V ,1..25V)
Organization(Depth , Width)
4M 16 = 8 M8
= 64 Mb
8M 16 = 16M8
= 128Mb
16M 16 = 32M 8 = 64M 4 = 256Mb
32M 16 = 64M 8 = 128M 4 = 512Mb
64M 16 = 128M 8 = 256M 4 = 1Gb
128M 16 = 256M 8 = 512M 4 = 2Gb
256M 16 = 512M 8 = 1024M4 = 4Gb
Note: M= Mono
Device Version
A = 1st Version B = 2nd Version
C = 3rd Version D = 4th Version
E = 5th Version F = 6th Version
G = 7th Version H = 8th Version
DH Special Type Option
I = Industrial Grade
B = Reduced Standby
H = Automotive Grade 2
A = Automotive Grade 3
Speed
SDRAM
75B = PC- 133 3-3-3
6K = PC- 166 3-3-3
DDR SDRAM
6K = DDR - 333 2.5-3-3
5T = DDR - 400 3-3-3
DDR2 SDRAM
5A = DDR2 - 400 3-3-3
37B = DDR2 - 533 4-4-4
3C = DDR2 - 667 5-5-5
25C/AC = DDR2 - 800 5-5-5
25D/AD = DDR2 - 800 6-6-6
BE = DDR2-1066 7-7-7
BD = DDR2-1066 6-6-6
DDR 3 SDRAM
AC = DDR3 - 800 5-5-5
AD = DDR3 - 800 6-6-6
BE = DDR3 - 1066 7-7-7
BF = DDR3 - 1066 8-8-8
CF = DDR3- 1333 8-8-8
CG = DDR3- 1333 9-9-9
DG = DDR3- 1600 9-9-9
DH = DDR3- 1600 10-10-10
DI = DDR3- 1600 11-11-11
EJ = DDR3- 1866 12-12-12
EK = DDR3- 1866 13-13-13
FK = DDR3- 2133 13-13-13
FL = DDR3- 2133 14-14-14
Package Code
RoHS + Halogen Free
S= TSOP(II )
N=78 -Ball BGA
P=96 -Ball BGA
E=60 -Ball BGA
J=68 -Ball BGA
M=92 -Ball BGA
U=71 -Ball BGA
Y=63 -Ball BGA
8=136-Ball BGA
G= DDR1 BGA / DDR2 84- Ball BGA
Version 1.3
09/ 2013
5 Nanya Technology Cooperation ©
All Rights Reserved.

5 Page





NT5CC128M8FN-DI arduino
DDR3(L) 1Gb SDRAM
NT5CB(C)128M8FN / NT5CB(C)64M16FP
Basic Functionality
The DDR3(L) SDRAM is a high-speed dynamic random access memory internally configured as an eight-bank DRAM.
The DDR3(L) SDRAM uses an 8n prefetch architecture to achieve high speed operation. The 8n prefetch architecture is
combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write
operation for the DDR3(L) SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and
two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write operation to the DDR3(L) SDRAM are burst oriented, start at a selected location, and continue for a burst
length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an Active
command, which is then followed by a Read or Write command. The address bits registered coincident with the Active
command are used to select the bank and row to be activated (BA0-BA2 select the bank; A0-A13 select the row). The
address bit registered coincident with the Read or Write command are used to select the starting column location for the
burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode ‘on the
fly’ (via A12) if enabled in the mode register.
Prior to normal operation, the DDR3(L) SDRAM must be powered up and initialized in a predefined manner. The following
sections provide detailed information covering device reset and initialization, register definition, command descriptions
and device operation.
RESET and Initialization Procedure
Power-up Initialization sequence
The Following sequence is required for POWER UP and Initialization
1. Apply power (REET is recommended to be maintained below 0.2 x VDD, all other inputs may be undefined). REET
needs to be maintained for minimum 200μs with stable power. CKE is pulled “Low” anytime before REETbeing
de-asserted (min. time 10ns). The power voltage ramp time between 300mV to VDDmin must be no greater than 200ms;
and during the ramp, VDD>VDDQ and (VDD-VDDQ) <0.3 Volts.
- VDD and VDDQ are driven from a single power converter output, AND
- The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one
side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to 0.95V max once
power ramp is finished, AND
- Vref tracks VDDQ/2.
OR
- Apply VDD without any slope reversal before or at the same time as VDDQ.
- Apply VDDQ without any slope reversal before or at the same time as VTT & Vref.
- The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one
side and must be larger than or equal to VSSQ and VSS on the other side.
2. After REETis de-asserted, wait for another 500us until CKE become active. During this time, the DRAM will start
internal state initialization; this will be done independently of external clocks.
3. Clock (CK, ) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes active.
Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be meeting. Also a NOP or
Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE registered
Version 1.3
09/ 2013
11 Nanya Technology Cooperation ©
All Rights Reserved.

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