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PDF TB62D612FTG Data sheet ( Hoja de datos )
| Número de pieza | TB62D612FTG | |
| Descripción | 24-Channel Constant-Current LED Driver | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TB62D612FTG
TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic
TB62D612FTG
24-Channel Constant-Current LED Driver of the 3.3-V and 5-V Power Supply Voltage Operation
The TB62D612FTG is a constant-current driver designed for LED and LED
display lighting.
The TB62D612FTG incorporates twenty-four channels of seven-bit PWM
dimming controllers and constant-current drivers. Twenty-four constant-current
drivers are divided into three blocks, each consisting of three drivers, and the
output current of each can be independently adjusted by the relevant external
resistor.
The TB62D612FTG is controlled using the SDA and SCLK input signals, and
capable of high-speed data transfers.
The TB62D612FTG can be set address with ID terminal. (Up to 64 address)
High-speed processing is capable by applying Bi-CMOS process.
The TB62D612FTG operates with a supply voltage of 3.3 V or 5 V.
P-WQFN36-0606-0.50-001
Weight: 0.083 g ( typ.)
1． Features
• Power supply voltages: VCC = 3.3 V/5 V
• Output drive capability and output count: 80 mA (max)× 24 channels
• Constant-current output range: 5 to 40 mA
• Voltage applied to constant-current output terminals: 0.4 V(min) (IOUT = 5 to 40 mA)
• Designed for common-anode LEDs
• The input interface is controlled by the SDA and SCLK signal lines
• Thermal shutdown (TSD)
• Logical Input signal voltage level: 3.3-V and 5-V CMOS interfaces (Schmitt trigger input)
• Maximum output voltage: 28 V
• Incorporating PWM control circuitry: Provides seven-bit PWM control.
• Driver identification: Up to 64 drivers can be controlled individually.
• Operating temperature range: Topr = −40 to 85 °C
• Package: P-WQFN36-0606-0.50-001
• Constant-current accuracy
Output Voltage
Current Accuracy Current Accuracy
Between Channels Between ICs
0.4 V
±3.0%
±6.0%
Output Current
15 mA
1 2012-07-23
1 page  
TB62D612FTG
6．Programming the TB62D612FTG
The TB62D612FTG can be programmed by the SDA and SCLK signals.
The TB62D612FTG should be programmed using one of the following formats: (1) Serial Packet Format in Normal Programming
Mode or (3) Serial Packet Format in Special Mode.
(1) Serial Packet Format in Normal programming Mode
【Typical】
Start Command Slave address
[11111111]
8 bits
Sub-address
(Channel select)
8 bits
Data byte
(PWM configuration)
8 bits
Period Command
[10000001]
・Normal programming Mode should be set as the following flow.
“Start Command” Æ “Slave address” Æ “Sub-address” Æ “Data byte” Æ “Period Command”
As for example of data input, refer to Page8.
・Input data from SDA signal is written to the shift register at the rising edge of SCLK every 8 bit.
This data is transferred at the falling edge of the eighth CLK. So, at the eighth CLK, data should be inputted to the falling edge.
Block diagram of data setting part
Data is transferred at
the falling edge of the
eighth SCLK.
Data
Byte
88ビbッitト
cカoウunンteタr
ＯＵＴ
R0
ＯＵＴ
G0
ＯＵＴ
B0
ＯＵＴ
R1
ＯＵＴ
B6
ＯＵＴ
R7
ＯＵＴ
G7
ＯＵＴ
B7
8bit 8bit 8bit 8bit
8bit 8bit 8bit 8bit
Term終in了alコcoマmンmドand
8bit
ﾃﾞｰDBRRﾀay0ﾊt0teaﾞｲﾄ
8bit
ﾃﾞｰDBGGﾀayﾊ00tteaﾞｲﾄ
8bit
ﾃﾞｰDBBBﾀya0ﾊt0teaﾞｲﾄ
8bit
ﾃﾞｰDBRRﾀyaﾊ11tteaﾞｲﾄ
8bit
ﾃﾞDｰaﾀtﾊaﾞｲﾄ
ByBt6e
8bit
ﾃﾞｰDBRRﾀyaﾊ77tteaﾞｲﾄ
8bit
ﾃﾞｰDBGGﾀay7ﾊt7teaﾞｲﾄ
8bit
ﾃﾞｰDBBBﾀay7ﾊt7teaﾞｲﾄ
8bit 8bit 8bit 8bit
8bit 8bit 8bit 8bit
SuサbブAアdドdレrスess
8bit
SlaスvレeーAブdアdドrレeスss
8bit
SDA
8b8itビsSッhトhシiifftフt--rトreeレsgジisiスsttタeerr
SCLK
In case of period command
SDA
Data is written to the shift register at the
rising edge of the SCLK.
Data is transferred at
the falling edge of the
eighth SCLK.
SCLK
5 2012-07-23
5 Page 
e) In case the period command mistakes.
TB62D612FTG
Transferring data B Start output
Internal PWM clock
Pattern 5
Start Data A
127
1 127 1
Start Data B Period
Input invalid term
Data B output
Outputting data A does not start at the rising edge of one internal clock which is just after the data A input. Outputting data B
starts at the rising edge of one internal PWM clock which is just after the data B input.
(7) Example of data input to the different ID.
a) In case the data B is inputted to slave (= 02h) just after the data A is inputted to slave (= 00h).
Transferring data A and data B. Start output
Internal PWM clock
Pattern 6
Start Slave=00h, Data A Period Start Slave=002h, Data B Period
Slave=00h output
Slave=02h output
127
1
Data A output
Data B output
Both data A and data B are outputted at the rising edge of one internal PWM clock which is just after the data A and the data B
inputs.
Pay attention that the IC does not operate according to the configuration while following patterns (patterns 7 and 8) are inputted.
b) In case period command after inputting data A to the slave (=00h) is missed or omitted or in case period command after
inputting data B to the slave (=02h) is missed or omitted.
Internal PWM clock
Pattern 7
Start Slave=00h, Data A Start Slave=02h, Data B
Slave=00h output
Slave=02h output
Data A is outputted. Data B is not outputted.
Transferring data A Start output
127 1
Data A output
c) In case start command is inputted after data B of pattern 7 is inputted.
Internal PWM clock
Pattern 8
Start Slave=00h, Data A Start Slave=02h, Data B Start
Slave=00h output
Slave=02h output
Data A is outputted. Data B is not outputted.
Transferring data A Start output
127 0
Data A output
11 2012-07-23
11 Page | ||
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| PDF Descargar | [ Datasheet TB62D612FTG.PDF ] | |
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