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Número de pieza | TCC8900 | |
Descripción | High Performance and Low-Power Processor | |
Fabricantes | Telechips | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de TCC8900 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! FULL
SPECIFICATION
TCC8900
High Performance and Low-Power Processor
For Digital Media Applications
TCC8900_FULL_SPEC
Rev. 1.03
Oct 09, 2009
1 page TCC8900
TCC8900_FULL_SPEC
High Performance and Low-Power Processor for Digital Media Applications
Oct 09, 2009
REVISION HISTORY
Revision History
Date
2008-12-11
2009-02-10
2009-02-25
2009-06-05
2009-08-07
2009-08-18
2009-09-04
2009-10-09
Revision
0.00
0.01
0.02
0.03
1.00
1.01
1.02
1.03
Description
* Initial Release
* The revision number of “PART 2. SMU & PMU” was changed to 0.01
* The revision number of “PART 3. GPIO” was changed to 0.01
* The revision number of “PART 4. CORE & MEMORY BUS” was changed to 0.01
* The revision number of “PART 5. IO BUS” was changed to 0.01
* The revision number of “PART 6. DDI BUS” was changed to 0.01
* The revision number of “PART 7. VIDEO BUS” was changed to 0.01
* The revision number of “PART 8. GRAPHIC BUS” was changed to 0.01
* The revision number of “PART 2. SMU & PMU” was changed to 0.02
* The revision number of “PART 3. GPIO” was changed to 0.02
* The revision number of “PART 4. CORE & MEMORY BUS” was changed to 0.02
* The revision number of “PART 5. IO BUS” was changed to 0.02
* The revision number of “PART 6. DDI BUS” was changed to 0.02
* The revision number of “PART 7. VIDEO BUS” was changed to 0.02
* The revision number of “PART 8. GRAPHIC BUS” was changed to 0.02
* The “CHIPSPEC” was appended.
* The revision number of “PART 2. SMU & PMU” was changed to 0.03
* The revision number of “PART 3. GPIO” was changed to 0.03
* The revision number of “PART 5. IO BUS” was changed to 0.03
* The revision number of “PART 6. DDI BUS” was changed to 0.03
* The revision number of “PART 7. VIDEO BUS” was changed to 0.03
* The revision number of “PART 8. GRAPHIC BUS” was changed to 0.03
* The revision number of “CHIPSPEC” was changed to 1.00
* The revision number of “PART 1. OVERVIEW” was changed to 1.00
* The revision number of “PART 2. SMU & PMU” was changed to 1.00
* The revision number of “PART 3. GPIO” was changed to 1.00
* The revision number of “PART 4. CORE & MEMORY BUS” was changed to 1.00
* The revision number of “PART 5. IO BUS” was changed to 1.00
* The revision number of “PART 6. DDI BUS” was changed to 1.00
* The revision number of “PART 7. VIDEO BUS” was changed to 1.00
* The revision number of “PART 8. GRAPHIC BUS” was changed to 1.00
* The revision number of “CHIPSPEC” was changed to 1.01
* The revision number of “CHIPSPEC” was changed to 1.02
* The revision number of “PART 2. SMU & PMU” was changed to 1.01
* The revision number of “PART 5. IO BUS” was changed to 1.01
* The revision number of “PART 6. DDI BUS” was changed to 1.01
* The revision number of “CHIPSPEC” was changed to 1.03
* The revision number of “PART 2. SMU & PMU” was changed to 1.02
* The revision number of “PART 4. CORE & MEMORY BUS” was changed to 1.01
* The revision number of “PART 5. IO BUS” was changed to 1.02
* The revision number of “PART 6. DDI BUS” was changed to 1.02
5
5 Page Oct 09, 2009
TABLE OF CONTENTS
TCC8900_CHIP_SPEC
TCC8900
High Performance and Low-Power Processor for Digital Media Applications
Figure 5.26 Write Cycle Timing ............................................................................................................................. 5-57
Figure 5.27 Read Cycle Timing ............................................................................................................................. 5-57
Tables
Table 1.1 TCC8900 Features .................................................................................................................................. 1-2
Table 2.1 ARM1176JZFS Processor........................................................................................................................ 2-7
Table 2.2 Video Controller ....................................................................................................................................... 2-8
Table 2.3 Camera Interface ..................................................................................................................................... 2-8
Table 2.4 Video Output Interface ............................................................................................................................. 2-9
Table 2.5 DAI/CDIF Controller............................................................................................................................... 2-10
Table 2.6 SPDIF Controller.................................................................................................................................... 2-10
Table 2.7 External Device Interface....................................................................................................................... 2-10
Table 2.8 USB 1.1 Host ......................................................................................................................................... 2-10
Table 2.9 USB 2.0 OTG(On-The-GO) ................................................................................................................... 2-10
Table 2.10 nano PHY for USB2.0 OTG and USB1.1 Host..................................................................................... 2-11
Table 2.11 External Host Interface......................................................................................................................... 2-11
Table 2.12 SD/MMC Controller.............................................................................................................................. 2-11
Table 2.13 Memory Stick Controller....................................................................................................................... 2-11
Table 2.14 Nand Flash Controller.......................................................................................................................... 2-12
Table 2.15 IDE interface ........................................................................................................................................ 2-12
Table 2.16 UART Interface .................................................................................................................................... 2-12
Table 2.17 GPSB Interface.................................................................................................................................... 2-13
Table 2.18 General DMA Controller....................................................................................................................... 2-13
Table 2.19 Vectored Interrupt Controller................................................................................................................ 2-13
Table 2.20 Timer.................................................................................................................................................... 2-13
Table 2.21 ADC ..................................................................................................................................................... 2-14
Table 2.22 Real Time Clock................................................................................................................................... 2-14
Table 3.1 Power/Ground Information..................................................................................................................... 3-15
Table 3.2 PWRGPIOC Group I/O Pin Description ................................................................................................. 3-16
Table 3.3 PWRGPIOF Group I/O Pin Description ................................................................................................. 3-17
Table 3.4 PWRGPIOE Group I/O Pin Description ................................................................................................. 3-18
Table 3.5 PWRGPIOA Group I/O Pin Description ................................................................................................. 3-19
Table 3.6 PWRADC Group I/O Pin Description ..................................................................................................... 3-20
Table 3.7 PWRETC Group I/O Pin Description ..................................................................................................... 3-20
Table 3.8 PWRGPIOD Group I/O Pin Description ................................................................................................. 3-21
Table 3.9 PWRGPIOB Group I/O Pin Description ................................................................................................. 3-22
Table 3.10 PWRMEMQ Group I/O Pin Description ............................................................................................... 3-23
Table 3.11 PWROSC Group I/O Pin Description ................................................................................................... 3-24
Table 3.12 PWRUSB33 Group I/O Pin Description ............................................................................................... 3-24
Table 3.13 PWRUSBH Group I/O Pin Description................................................................................................. 3-24
Table 3.14 PWRRTC Group I/O Pin Description ................................................................................................... 3-24
Table 3.15 PWRSATAOSC Group I/O Pin Description .......................................................................................... 3-24
Table 3.16 PWRSATA Group I/O Pin Description .................................................................................................. 3-24
Table 3.17 PWRHDMIOSC Group I/O Pin Description.......................................................................................... 3-24
Table 3.18 PWRHDMI Group I/O Pin Description ................................................................................................. 3-24
Table 3.19 PWRLVDS Group I/O Pin Description.................................................................................................. 3-24
Table 3.20 PWRDAC Group I/O Pin Description ................................................................................................... 3-24
Table 3.21 TCC8900 I/O Type ............................................................................................................................... 3-25
Table 5.1 Recommended Operating Conditions.................................................................................................... 5-30
Table 5.2 Recommended Operating Frequency.................................................................................................... 5-31
Table 5.3 Peak Power Consumption ..................................................................................................................... 5-34
Table 5.4 DC Electrical Specification for General I/O ............................................................................................ 5-35
Table 5.5 DC Electrical Characteristics for PLL0................................................................................................... 5-36
Table 5.6 AC Electrical Characteristics for PLL0 ................................................................................................... 5-36
Table 5.7 DC Electrical Characteristics for PLL1/2/3 ............................................................................................. 5-36
Table 5.8 AC Electrical Characteristics for PLL1/2/3 ............................................................................................. 5-36
Table 5.9 DC Electrical Characteristics for DAC.................................................................................................... 5-37
Table 5.10 DC Electrical Characteristics for ADC.................................................................................................. 5-38
Table 5.11 AC Electrical Characteristics for ADC................................................................................................... 5-38
Table 5.12 DC Electrical Characteristics for HDMI PHY........................................................................................ 5-39
Table 5.13 AC Electrical Characteristics for HDMI Oscillator................................................................................. 5-39
Table 5.14 DC Electrical Characteristics for LVDS ................................................................................................ 5-40
Table 5.15 AC Electrical Characteristics for LVDS................................................................................................. 5-40
Table 5.16 DC Electrical Characteristics for SATA ................................................................................................ 5-41
Table 5.17 AC Electrical Characteristics for SATA Oscillator ................................................................................. 5-41
Table 5.18 AC Electrical Characteristics for SATA TX/RX...................................................................................... 5-41
Table 5.19 Timing Parameters for Each Symbol ................................................................................................... 5-42
6
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet TCC8900.PDF ] |
Número de pieza | Descripción | Fabricantes |
TCC8900 | (TCC8900 - TCC8902) Development Board | ETC |
TCC8900 | High Performance and Low-Power Processor | Telechips |
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TCC8902 | (TCC8900 - TCC8902) Development Board | ETC |
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