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PDF VT1702S Data sheet ( Hoja de datos )
| Número de pieza | VT1702S | |
| Descripción | High Definition Audio Codec | |
| Fabricantes | VIA | |
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Data Sheet
VT1702S
High Definition Audio Codec
November 13, 2009
(Released under Creative Commons License)
Preliminary Revision 1.0
1 page  
Data Sheet
VT1702S High Definition Audio Codec
1.2 Software Features
y Meets Microsoft WLK1.2 and conforms
to the requirements of Windows
Hardware Quality Labs testing (WHQL)
y Functions of Speaker Device
– Equalizer (EQ)
– Room Correction (RC)
– Bass Management (BM)
– Environment Modeling (EM)
– Loudness Equalization (LE)
– Speaker Fill (SF)
y General features for Mic-Array
Application
– Acoustic Echo Cancellation (AEC)
– Noise Suppression (NS)
– Beam Forming (BF)
y Recording Control for Microphone
Input
y Digital Output Control UI
y VIA Vendor Driver Support
y Supports various operating systems
– Microsoft Windows 2000
– Microsoft Windows Server 2003
– Microsoft Windows XP
– Microsoft Windows Vista
(32-bit/64-bit)
– Microsoft WinCE4.2 / 5.0 / 6.0
– Linux (Fedora Core 7, 8 / Suse SLED
Desktop 10SP1 / UBUNTU 7.1 /
Redhat)
y Optional Sound Effect
– QSound 3D audio effects
– DTS CONNECT / DTS Surround
Sensation
– Dolby1 PCEE program
– Creative audio program
– 3rd party Microphone Array technology
y Optional Software Feature
– Karaoke Mode for Home Entertainment
– Dynamic range control with adjustable
parameters
1 Supply of this Implementation of Dolby technology
does not convey a license nor imply a right under any
patent, or any other industrial or intellectual property
right of Dolby Laboratories, to use this Implementation
in any finished end-user or ready-to-use final product.
It is hereby notified that a license for such use is required
from Dolby Laboratories.
2
5 Page 
Data Sheet
VT1702S High Definition Audio Codec
8
6 High Definition Audio Link Protocol
6.1 Link Signaling
The link protocol defines the digital serial interface that connects High Definition Audio codec to the audio
controller, and is not compatible with the previous AC97 protocol. The link is controller synchronous,
based on a fixed 24MHz BITCLK and is purely isochronous without any flow control.
Figure 3 – High Definition Audio Link Conceptual View
6.2 Signal Definitions
Table 3 – High Definition Audio Link Conceptual View
Signal Name Source
Type Description
BITCLK
Controller
I
24MHz clock.
SYNC
Controller
I
Global 48KHz Frame Sync and outbound tag signal.
SDO
Controller
I
Bussed serial data output from controller.
SDI
Codec &
I/O Point-to-point serial data. Controller has a weak pull down.
controller
RESETN
Controller I
Global active low reset signal.
BITCLK is the 24MHz clock sourced from the controller and connecting to all codec on the link.
SYNC marks input and output frame boundaries (Frame Sync) as well as identifying outbound data
streams (stream tags). SYNC is always sourced from the controller and connects to all codec on the link.
SDO is driven by the controller to all codec on the link. Compared with AC97, the SDO is double pumped
with respect to both rising and falling edges of BITCLK in order to increase the bandwidth required for
High Definition Audio link.
SDI is a point-to-point data signal driven by the codec to the controller. Because the bandwidth
requirement is not that high compared to SDO, data is single pumped with respect to only the rising edge
of BITCLK. The controller is required to implement weak pull-down on all SDI signals.
RESETN is sourced from the controller and connects to all codec on the link. Assertion of RESETN results
I null link interface logic being reset to Default power on state.
11 Page | ||
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