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PDF CCG1 Data sheet ( Hoja de datos )

Número de pieza CCG1
Descripción USB Type-C Port Controller
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! CCG1 Hoja de datos, Descripción, Manual

PRELIMINARY
CCG1 Datasheet
USB Type-C Port Controller with
Power Delivery
General Description
CCG1 provides a complete USB Type-C and USB Power Delivery port control solution. The scalable and reconfigurable core
architecture of CCG1 enables a base Type-C solution that can scale to a complete 100-W USB Power Delivery with Alternate Mode
mux support. CCG1 is also a Type-C cable ID IC for active and passive cables. The ARM® Cortex®-M0 CPU based core can use
common open source firmware or custom solutions developed with common libraries and APIs. CCG1 is the CC controller that detects
connector insert, plug orientation, and VCONN switching signals. CCG1 makes it easier to add USB Power Delivery to any architecture
because it provides the control signals to manage external VBUS and VCONN power management solutions as well as external mux
controls for most single cable-docking solutions. CCG1's packaging options, and programmability, enables any USB Type-C and USB
Power Delivery solution.
Applications
Type-C Support
Notebooks, tablets, monitors, docking stations
Power adapters, USB Type-C cables
Features
Integrated transceiver (BB PHY)
Supports up to two USB ports with PD
Supports routing of all protocols through an external mux
PD Support
32-bit MCU Subsystem
48-MHz ARM Cortex-M0 CPU with 32-KB flash and 4-KB
SRAM
Supports Provider and Consumer roles
Supports all power profiles
Low power operation
Integrated analog blocks
1.8-V to 5.5-V operation
12-bit, 1-Msps ADC for VBUS voltage and current monitoring Sleep 1.3 mA, Deep Sleep 1.3 uA
Dynamic overcurrent and overvoltage protection
Packages
Integrated digital blocks
40-pin QFN
Two configurable 16-bit TCPWM blocks
One I2C master or slave
16-pin SOIC
28-pin SSOP
35-ball wafer-level CSP (WLCSP)
Figure 1. CCG1 Block Diagram [1, 2, 3, 4, 5, 6]
CCG1: USB Type-C Port Controller with PD
MCU Subsystem
Integrated Analog Blocks
IDAC
ADC
CORTEX-M0
48 MHz
Flash
(32KB)
SRAM
(4KB)
Serial Wire Debug
Comparators
Integrated Digital Blocks
TCPWM1
SCB2
(I2C, SPI, UART)
Profiles and
Configurations
BB3 MAC
BB3 PHY
I/O Subsystem
CC
Rp4, Rd5,
Ra6
Control
VBUS
Control
VCONN
Control
Voltage
Select
MUX
Control
Current
Control
Device
Detect
VBUS
Sense
VCONN
Sense
GPIO
Port
Notes
1. Timer, counter, pulse-width modulation block.
2. Serial communication block configurable as UART, SPI, or I2C.
3. Base band.
4. Termination resistor denoting a Downstream Facing Port (DFP).
5. Termination resistor denoting a Upstream Facing Port (UFP).
6. Termination resistor denoting an Electronically Marked Cable Assembly (EMCA).
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-93639 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 4, 2015

1 page




CCG1 pdf
PRELIMINARY
CCG1 Datasheet
Following is the pin definition for 28-pin SSOP for the Power Adapter application. Refer to Table 23 for part numbers to package
mapping.
Table 2. Pin Definitions for 28-pin SSOP for Power Adapter Application
Functional Pin Name
28-pin SSOP Pin
#
Type
Description
CC_RD
1 O Open Drain signal to connect RD to CC 1 line
z: RD not connected
0: RD connected
NC 2 I No Connect
VBUS_P_CTRL
3 O Full rail control signal for enabling/disabling Provider load FET
GPIO_1
4 I General Purpose IOs
NC 5 O No Connect
CC_RP
6 I Open Source signal to connect RP to CC 1 line
z: RP not connected
1: RP connected
GPIO_3
7 I General Purpose IOs
VREF_5V
8 O Open drain reference control signal for VBUS value of 5 V
0: VBUS_VREF is a reference for VBUS = 5 V
z: VBUS_VREF is NOT a reference for VBUS = 5 V
CS_P
9 I Low Side Current Sense
GPIO_2
10 I General Purpose IOs
CC_TX
11 O Configuration Channel TX
VREF_12V
12 I/O Open drain reference control signal for VBUS value of 12 V
0: VBUS_VREF is a reference for VBUS = 12 V
z: VBUS_VREF is NOT a reference for VBUS = 12 V
SWD_IO
13 I/O SWD IO
SWD_CLK
14 I SWD Clock
VREF_20V
15 I/O Open drain reference control signal for VBUS value of 20 V
0: VBUS_VREF is a reference for VBUS = 20 V
z: VBUS_VREF is NOT a reference for VBUS = 20 V
VSEL1
16 I/O Voltage Select signal 1 for selecting the output voltage / PWM signal
for AC power adapters. Can provide 0%, 33%, 66%, or 100% duty
cycle
VSEL2
17 I/O Voltage Select signal 2 for selecting output voltage
CC_TXEN
18 O Open Drain signal to enable TX function on the CC 1 line
0: TX enabled
z: TX disabled
CC_RX
19 I Configuration Channel RX
CC_VREF
20 I Data reference signal for CC line (0.55 V)
VBUS_VMON
21 I VBUS Over-voltage Protection monitoring signal
VBUS_VREF
22 I Data reference signal for CC lines
VBUS_OK
23 O VBUS_OK = 1-VBUS Voltage ok
VBUS_OK = 0-VBUS Over voltage detected
VBUS_DISCHARGE
24 O Signal used for discharging VBUS line during voltage change
XRES
25 I Reset
VCCD
26 POWER Connect 1 µF Capacitor between VCCD and Ground
VDDD
27 POWER 3.3 V Supply
VSSA
28 GND Ground
Document Number: 001-93639 Rev. *D
Page 5 of 36

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CCG1 arduino
Pinouts
PRELIMINARY
Figure 2. 40-pin QFN Pinout
CCG1 Datasheet
MUXSEL_1
MUXSEL_2
CC1_CTRL
CC2_CTRL
MUXSEL_3
MUXSEL_4
CS_P
CS_M
VSS
CC1
1
2
3
4
5
6
7
8
9
10
QFN
(Top View)
30 XRES
29 CC2_VCONN_CTRL
28 CC2_RP
27 CC2_RD
26 CC2
25 VBUS_DISCHARGE
24 CC1_VCONN_CTRL
23 CC1_RP
22 CC1_RD
21 DEV_DET
Figure 3. 16-pin SOIC Pinout
SWD_CLK
VBUS_P_CTRL
VBUS_VMON
VBUS_VREF
XRES
VCCD
VSSD
VDDD
1
2
3
4
5
6
7
8
SOIC
(Top View)
16 SWD_IO
15 CC
14 VSEL2
13 VSEL1
12 CS
11 CC_CTRL
10 CC_VREF/VBUS_DISCHARGE
9 VSSA
Figure 4. 28-pin SSOP Pinout
CC_RD
NC
VBUS_P_CTRL
GPIO_1
NC
CC_RP
GPIO_3
VREF_5V
CS_P
GPIO_2
CC_TX
VREF_12V
SWD_IO
SWD_CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
(Top View)
28 VSSA
27 VDDD
26 VCCD
25 XRES
24 VBUS_DISCHARGE
23 VBUS_OK
22 VBUS_VREF
21 VBUS_VMON
20 CC_VREF
19 CC_RX
18 CC_TXEN
17 VSEL2
16 VSEL1
15 VREF_20V
Document Number: 001-93639 Rev. *D
Page 11 of 36

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