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PDF 25Q32FV Data sheet ( Hoja de datos )

Número de pieza 25Q32FV
Descripción W25Q32FV
Fabricantes Winbond 
Logotipo Winbond Logotipo

25Q32FV image


1. Serial Flash Memory - Winbond






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No Preview Available ! 25Q32FV Hoja de datos, Descripción, Manual

W25Q32FV
3V 32M-BIT
SERIAL FLASH MEMORY WITH
DUAL/QUAD SPI & QPI
Publication Release Date: OCtober 15, 2012
Revision D

1 page




25Q32FV pdf
W25Q32FV
10.4 8-Pad WSON 8x6-mm (Package Code ZE)....................................................................... 89
10.5 16-Pin SOIC 300-mil (Package Code SF) .......................................................................... 90
10.6 8-Pin PDIP 300-mil (Package Code DA) ............................................................................ 91
10.7 24-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 ball array).......................................... 92
10.8 24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 ball array)............................................. 93
11. ORDERING INFORMATION .......................................................................................................... 94
11.1 Valid Part Numbers and Top Side Marking ........................................................................ 95
12. REVISION HISTORY...................................................................................................................... 96
Publication Release Date: OCtober 15, 2012
- 4 - Revision D

5 Page





25Q32FV arduino
W25Q32FV
4. PIN DESCRIPTIONS
4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program or
write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS
input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure
58). If needed a pull-up resister on the /CS pin can be used to accomplish this.
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25Q32FV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use
the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising
edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read
data or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge of
CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.
When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.
4.3 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status
Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be
hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O,
the /WP pin function is not available since this pin is used for IO2. See Figure 1a-c for the pin
configuration of Quad I/O operation.
4.4 HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low,
while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored
(don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be
useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the
QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is
used for IO3. See Figure 1a-e for the pin configuration of Quad I/O operation.
4.5 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Operations")
4.6 Reset (/RESET)
The /RESET pin allows the device to be reset by the controller. For 8-pin packages, when QE=0, the IO3
pin can be configured either as a /HOLD pin or as a /RESET pin depending on Status Register setting.
When QE=1, the /HOLD or /RESET function is not available for 8-pin configuration. On the 16-pin SOIC
package, a dedicated /RESET pin is provided and it is independent of QE bit setting.
- 10 -
Publication Release Date: OCtober 15, 2012
Revision D

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