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PDF THCV234 Data sheet ( Hoja de datos )
| Número de pieza | THCV234 | |
| Descripción | HS High-speed video data transmitter and receiver | |
| Fabricantes | THine Electronics | |
| Logotipo |  |
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THCV233-THCV234_Main-Link_Rev.2.12_E
THCV233 and THCV234 Main-Link
V-by-One®HS High-speed video data transmitter and receiver with bi-directional transceiver
1. General Description
THCV233 and THCV234 are V-by-One® HS High-speed
video data transmitter/receiver with bi-directional transceiver.
They convey not only video data (Main-Link), but also
bi-directional system control data (Sub-Link) that is driven
by 2-wire serial interface. HOST CPU-side of Sub-Link is
selectable on each device and the other side of Sub-Link*
integrates I/O expander.
THCV233-234 system is able to watch and control
peripheral devices via 2-wire serial interface or GPIOs. They
also can report interrupt events caused by change of GPIO
inputs and internal statuses.
2. Features
LVDS Input internal termination
CORE 1.8V, LVDS 3.3V
Package: 48 pin QFN
EU RoHS Compliant
Main-Link
Data width selectable: 24/32 bit
Single/Dual Link selectable
AC coupling
Wide frequency range
CDR requires no external freq. reference
Supports Spread Spectrum Clocking:
Up to 30kHz/0.5%(center spread)
Sub-Link
Concerning Sub-Link and GPIO detail specification,
please refer to “THCV233-THCV234_Sub-Link”.
Si/So:Single-in/Single-out, Si/Do:Single-in/Dual-out
Si/DDo:Single-in/Distributed Dual-out
Di/So:Dual-in/Single-out, Di/SSo:Dual-in/Selected Single-out
Table 1
Product
THCV233
THCV234
TMP
VDL Width Link LVDS Clock Freq.
Si/So 9MHz to 100MHz
0°C~
70°C
24bit Si/DDo 20MHz to 100MHz
Si/Do 40MHz to 100MHz
Si/So 9MHz to 85MHz
32bit Si/DDo 20MHz to 85MHz
1.62V~
1.98V
Si/Do 40MHz to 85MHz
Si/So 9MHz to 100MHz
24bit Si/DDo 20MHz to 100MHz
Si/Do 40MHz to 100MHz
Si/So 9MHz to 75MHz
32bit Si/DDo 20MHz to 75MHz
-40°C~
105°C
Si/Do 40MHz to 75MHz
Si/So 9MHz to 100MHz
1.7V~
1.98V
24bit Si/DDo 20MHz to 100MHz
Si/Do 40MHz to 100MHz
Si/So 9MHz to 81MHz
32bit Si/DDo 20MHz to 81MHz
Si/Do 40MHz to 81MHz
Si/So 9MHz to 100MHz
0°C~
70°C
1.62V~
1.98V
24bit Di/SSo
Di/So
Si/So
20MHz to 100MHz
40MHz to 100MHz
9MHz to 85MHz
32bit Di/SSo 20MHz to 85MHz
Di/So 40MHz to 85MHz
Si/So 9MHz to 95MHz
-40°C~
105°C
1.7V~
1.98V
24bit Di/SSo 20MHz to 95MHz
Di/So 40MHz to 95MHz
Si/So 9MHz to 71.25MHz
32bit Di/SSo 20MHz to 71.25MHz
Di/So 40MHz to 71.25MHz
3.Block Diagram
TLA +/-
・
・
・
TLE +/-
TLCLK +/-
THCV233
・
・
・
TX0P RX0P
TX0N RX0N
TX1P RX1P
TX1N RX1N
THCV234
RLA +/-
・・
・・
・・
RLE +/-
RLCLK +/-
OSC
GPIO * 4
Controls
TCMP RCMP
TCMN RCMN
OSC
Controls
GPIO * 5
2-wire serial I/F
Copyright©2016 THine Electronics, Inc.
Figure 1
2-wire serial I/F
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THCV233-THCV234_Main-Link_Rev.2.12_E
Pin Name
MSSEL
AIN [1:0]
Pin #
12
34,33
THCV233 Pin Description (Continued)
Type*
Description
Master-side/Slave-side selector for Sub-Link and 2-wire serial interface.
I
H : Sub-Link Slave side (inside 2-wire serial I/F is master), L : Sub-Link Master side (inside 2-wire serial I/F is slave)
Sub-Link Master is connected to HOST MPU.
Forbid the same setting between THCV233 and THCV234.
Address setting for 2-wire serial interface.
When using 2-wire serial interface, it must be set the same value as THCV234's one.
AIN[1:0] =LL : 7'b0001011
I =LH : 7'b0110100
=HL : 7'b1110111
=HH : Reserved (Forbidden)
MODE [1:0]
IOSEL
PDN [1:0]
32,31 I
28 I
26,25 I
Operation mode select input for Main-Link.
MODE[1:0] =LL : Single-in/Distribution dual-out
=LH : Single-in/Single-out
=HL : Single-in/Dual-out
=HH : Reserved (Forbidden)
HTPDN, LOCKN pin enable input for Main-Link.
H : HTPDN, LOCKN pin disable (GPIO[1:0] enable), L : HTPDN, LOCKN pin enable (GPIO[1:0] disable)
When IOSEL inputs H, HTPDN and LOCKN state in THCV234 are brought by Sub-Link.
Power down Schmitt input.
PDN[1]: For Sub-Link power down control (2-wire serial interface + Sub-Link)
H: Normal operation, L: Power down
PDN[0]: For Main-Link power down control (LVDS-Rx + Main-Link)
H: Normal operation, L: Power down
PRE
29
I
Pre-Emphasis level select input for Main-Link.
H : 100%, L : 0%
COL
3
I
Data width setting for Main-Link.
H : 24bit, L : 32bit
BET
27
I
Field-BET entry.
H : Field BET Operation, L : Normal Operation
LAVDH
LAGND
CAVDL
CAGND
CPVDL
VDD
VSS
EXPGND
*Type symbol
1,36 P33
2,35 GND
22,14 P18
21,18,15 GND
13 P18
7,30 P18
6 GND
49 GND
LVDS power supply (3.3V)
LVDS GND
High-speed signal analog power supply (1.8V)
High-speed signal analog GND
High-speed signal PLL power supply (1.8V)
Logic power supply (1.8V)
Logic GND
EXPOSED PAD GND
I=3.3V CMOS input, B= CMOS Bi-directional buffer, BO= OpenDrain CMOS Bi-directional buffer
LI=LVDS input, CO=CML output, CB=CML Bi-directional buffer
P33=Power 3.3V, P18=Power 1.8V, GND=GND
Please refer to “THCV233-THCV234_Sub-Link” data sheet about Sub-Link and GPIO.
Copyright©2016 THine Electronics, Inc.
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THCV233-THCV234_Main-Link_Rev.2.12_E
Data Enable Requirement (DE)
There are some requirements for DE signal as described in Figure 3, Figure 4 Figure 14 and Table 31.
If DE=Low, control data of same cycle and particular assigned data bit ‘CTL’ except the first and the last pixel are
transmitted. Otherwise video data are transmitted during DE=High.
Control data from receiver in DE=High period are previous data of DE transition. See Figure 4.
The length of DE being low and high is at least 2 clock cycles long, as described in Figure 14 and Table 31.
Data Enable must be toggled like High -> Low -> High at regular interval.
THCV233
Data bit : R/G/B, CONT
H
Control bit : V,HSYNC
Data bit : CTL*
DE
L
THCV234 DE=H R/G/B,CONT
DE=L, CTL* except the 1st and the last pixel
other R/G/B,CONT=Low Fixed
R/G/B,
CONT,
CTL
DE=H, V,HSYNC=Fixed
DE=L, V,HSYNC
V,
HSYNC
DE
*CTL are particular assigned bit among R/G/B, CONT that can carry arbitrary data during DE=Low period.
Figure 3 Conceptual diagram of the basic operation of the chipset
DE input via LVDS
DE=High
Active period
DE=Low
Blanking period
Data : Low fixed
H, V : Keep the last data of blanking period
Data : Particular assigned bit ‘CTL’ is transmitted except the
first and the last pixel of Blanking period. / Others are Low fixed.
THCV233
input
TLn +/-
n=A,B,D,E
654321065432106543210654321065432106543210
TLC +/-
D
E
V
H
3
2
1
0
D
E
V
H
3
2
1
0
D
E
V
H
3
2
1
0
D
E
V
H
3
2
1
0
D
E
V
H
3
2
1
0
D
E
V
H
3
2
1
0
TLCLK +/-
Indefinite region
THCV234
output
RLn +/-
n=A,B,D,E
654321065432106543210654321065432106543210
RLC +/-
H L L L H HV H 3 2 1 0
VH3 2 1 0
VH3 2 1 0
VH3 2 1 0
VH3 2 1 0
VH3 2 1 0
RLCLK +/-
ALNOUT
(CMOS)
tRALN
Typ;5tTCIP/7
Indefinite region
±3/7tTCIP
tRALN
Typ;5tTCIP/7
Indefinite region
±3/7tTCIP
Figure 4 Data bit and control bit transmission when DE is from LVDS (default)
Copyright©2016 THine Electronics, Inc.
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| PDF Descargar | [ Datasheet THCV234.PDF ] | |
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