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PDF Z8030 Data sheet ( Hoja de datos )
| Número de pieza | Z8030 | |
| Descripción | Communications Controller | |
| Fabricantes | Zilog | |
| Logotipo |  |
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Zilog
Z8030 Z8000®
Z-SCC Serial
Communications Controller
Product
Specification
Features
General
Description
• Two independent, 0 to 1.5M bit/second, full-
duplex channels, each with a separate crystal
OSCillator, baud rate generator, and Digital
Phase-Locked Loop for clock recovery.
• Multi-protocol operation under program
control; programmable for NRZ, NRZI, or
FM data encoding.
• Asynchronous mode with five to eight bits
and one, one and one-half, or two stop bits
per character; programmable clock factor;
break detection and generation; parity,
overrun, and framing error detection.
• Synchronous mode with internal or external
character synchronization on one or two
The Z8030 Z-SCC Serial Communications
Controller is a dual-channel, multi-protocol
data communications peripheral designed for
use with the Zilog Z-Bus. The Z-SCC functions
as a serial-to-parallel, parallel-to-serial con-
verter/controller. The Z-SCC can be software-
configured to satisfy a wide variety of serial
April 1985
synchronous characters and CRC genera-
tion and checking with CRC-16 or
CRC-CCITT preset to either Is or Os.
• SDLC/HDLC mode with comprehensive
frame-level control, automatic zero insertion
and deletion, I-field residue handling, abort
generation and detection, CRC generation
and checking, and SDLC Loop mode
operation.
• Local Loopback and Auto Echo modes.
• 1.544M bit/second Tl digital trunk compatible
version available.
communications applications. The device con-
tains a variety of new, sophisticated internal
functions including on-chip baud rate
generators, Digital Phase-Locked Loops, and
crystal oscillators that dramatically reduce the
need for external logic.
2016-001,002
ADDRESS'
DATA BUS
AD,
TxDA
} SERIAL
AD, RIlOA _ _ DATA
AD, TRxCA ........-} CHANNEL
AD, RTxCA .--- CLOCKS
AD,
AD, CHANNEL
AD, CONTROLS
FOR MODEM,
ADo DMA,OR
As OTHER
OS
R/W
es,
} SERIAL
_ _ DATA
esc
INT
INTACK
lEI
lEO
-\IRTxes
._...._...
I\
CHANNEL
CLOCKS
SYNCe
WIREOB
DTR/REQB
RlSB
CHANNEL
CONTROLS
FDOMRAM,OORDEM,
Z8030 else __ OTHER
z·scc DeDS
CH·A
CH·B
ttt
+5V GND PCLK
Figure I. Pin Funcllons
AD,
AD,
AD,
AD,
iNT
lEO
lEi
INTACK
+sv
WIREQA
SYNCA
RheA
RIlOA
TRxCA
hDA
OTR/REQA
RlSA
elSA
DeCA
PClK
ADO
39 AD,
38 AD,
37 AD,
36 OS
35 As
34 RIW
Z8030
z·scc
11
33
32
31
30
eso
es,
GND
W/REoe
12 29 SYNCe
"13 RTxCB
37 RKOB
26 TRlleB
16 25 1)(D8
24 DTRIREQB
18 23 Rlse
19 22 elSS
21 DC De
Figure 2. 40-pin Dual-In-Line Package (DIP).
Pin Assignments
631
1 page  
Functional
Description
(Continued)
bit time after a Low level is detected on ihe
receive data input (RxOA or RxOB in
Figure I). If the Low does not persist (as in the
case of a transient), the character assembly
process does not start.
Framing errors and overrun errors are
detected and buffered together with the partial
character on which they occur. Vectored inter-
rupts allow fast servicing or error conditions
using dedicated routines. Furthermore, a
built-in checking process avoids the interpreta-
tion of a framing error as a new start bit: a
framing error results in the addition of one-half
a bit time to the point at which the search for
the next start bit begins.
The Z-SCC does not require symmetric
transmit and receive clock signals-a feature
allowing use of the wide variety of clock
sources. The transmitter and receiver can
handle data at a rate of I, 1/16, 1/32, or 1/64
of the clock rate supplied to the receive and
transmit clock inputs. In Asynchronous modes,
the SYNC pin may be programmed as an input
used for functions such as monitoring a ring
indicator.
Synchronous Modes. The Z-SCC supports both
byte-oriented and bit-oriented synchronous
communication. Synchronous byte-oriented
protocols can be handled in several modes,
allowing character synchronization with a 6-bit
or 8-bit synchronous character (Monosync),
any 12-bit synchronization pattern (Bisync), or
with an external synchronization signal.
Leading synchronous characters can be
removed without interrupting the CPU.
Five- or 7-bit synchronous characters are
detected with 8- or 16-bit patterns in the
Z-SCC by overlapping the larger pattern
across multiple incoming synchronous
characters as shown in Figure 4.
CRC checking for Synchronous byte-
oriented modes is delayed by one character
time so that the CPU may disable CRC check-
ing on specific characters. This permits the
implementation of protocols such as
IBM Bisync.
Both CRC-16 (X16 + XI5 + X2 + I) and
CCITT (X16 + Xl2 + X5 + I) error checking
polynomials are supported. Either polynomial
may be selected in all Synchronous modes.
Users may preset the CRC generator and
checker to all Is or all as. The Z-SCC also
provides a feature that automatically transmits
CRC data when no other data is available for
transmission. This allows for high speed
transmissions under OMA control, with no
need for CPU intervention at the end of a
message. When there is no data or CRC to
send in Synchronous modes, the transmitter
inserts 6-,8-, or 16-bit synchronous
characters, regardless of the programmed
character length.
The Z-SCC supports Synchronous bit-
oriented protocols, such as SOLC and HOLC,
by performing automatic flag sending, zero in-
sertion, and CRC generation. A special com-
mand can be used to abort a frame in transmis-
sion. At the end of a message, the Z-SCC
automatically transmits the CRC and trailing
flag when the transmitter underruns. The
transmitter may also be programmed to send
an idle line consisting of continuous flag
characters or a steady marking condition.
If a transmit underrun occurs in the middle
of a message, an external/status interrupt
warns the CPU of this status change so that an
abort may be issued. The Z-SCC may also be
programmed to send an abort itself in case of
an underrun, relieving the CPU of this task.
One to eight bits per character can be sent,
allowing reception of a message with no prior
information about the character structure in
the information field of a frame.
The receiver automatically acquires syn-
chronization on the leading flag of a frame in
SOLC or HOLC and provides a synchroniza-
tion signal on the SYNC pin (an interrupt can
also be programmed). The receiver can be
programmed to search for frames addressed by
a single byte (or four bits within a byte) of a
user-selected address or to a global broadcast
address. In this mode, frames not matching
either the user-selected or broadcast address
are ignored. The number of address bytes can
be extended under software control. For
receiving data, an interrupt on the first
received character, or an interrupt on every
character, or on special condition only (end-
of-frame) can be selected. The receiver
automatically deletes all as inserted by the
transmitter during character assembly. CRC is
also calculated and is automatically checked to
validate frame transmission. At the end of
transmission, the status of a received frame is
available in the status registers. In SOLC
mode, the Z-SCC must be programmed to use
the SOLC CRC polynomial, but the generator
and checker may be preset to all Is or all as.
~YNC
SYN9
5 BITS
.--'-..
I SYNC
'-v---'
8
V
16
DATA
DATA
DATA
DATA
Figure 4. Detecting 5- or 7-BIt Synchronous Characters
2016·005
635
5 Page 
Architecture
(Continued)
formats, synchronization, and validation for
data transferred to and from the channel inter-
face. The modem control inputs are monitored
by the control logic under program control.
All of the modem control signals are general-
purpose in nature and can optionally be used
for functions other than modem control.
The register set for each channel includes
ten control (write) registers, two sync
character (write) registers, and four status
(read) registers. In addition, each baud rate
generator has two (read/write) registers for
holding the time constant that d£(ermines the
baud rate. Finally, associated with the inter-
rupt logic is a write register for the interrupt
vector accessible through either channel, a
write-only Master Interrupt Control register
and three read registers: one containing the
vector with status infomation (Channel B only),
one containing the vector without status
(Channel A only), and one containing the
Interrupt Pending bits (Channel A only).
The registers for each channel are
designated as follows:
WRO-WRI5 - Write Registers 0 through 15.
RRO-RR3, RRIO, RRI2, RRI3, RRI5 - Read
Registers 0 through 3, 10, 12, 13, 15.
Table I lists the functions assigned to each
read or write register. The Z-SCC contains
only one WR2 and WR9, but they can be
accessed by either channel. All other registers
are paired (one for each channel).
Data Path. The transmit and receive data path
illustrated in Figure 9 is identical for both
channels. The receiver has three 8-bit buffer
registers in an FIFO arrangement, in addition
to the 8-bit receive shift register. This scheme
creates additional time fdr the CPU to service
an interrupt at the beginning of a block of
high speed data. Incoming data is routed
through one of several paths (data or CRC)
depending on the selected mode (the character
length in Asynchronous modes also determines
the data path).
The transmitter has an 8-bit Transmit Data
Programming The Z-SCC contains 13 write registers in
each channel that are programmed by the
system separately to configure the functional
personality of the channels. All of the registers
in the Z-SCC are directly addressable. How
the Z-SCC decodes the address placed on the
address/data bus at the beginning of a Read or
Write cycle is controlled by a command issued
in WROB. In the Shift Right mode the channel
select A/B is taken from ADo and the state of
ADs is ignored. In the Shift Left mode AlB is
taken from ADs and the state of ADo is
buffer register loaded from the internal data
bus and a 20-bit Transmit Shift register that
can be loaded either from the synchronous
character registers or from the Transmit Data
register. Depending on the operational mode,
outgoing data is routed through one of four
main paths before it is transmitted from the
Transmit Data output (TxD)
RRO
RRI
RR2
RR3
RR8
RRIO
RR 12
RR13
RRl5
Read Register Functions
Transmit/Receive buffer status and External status
Special Receive Condition status
Modified interrupt vector (Channel B only)
Unmodified interrupt vector (Channel A only)
Interrupt Pending bits (Channel A only)
Receive bulfer
Miscellaneous status
Lower byte of baud rate generator time constant
Upper byte of baud rate generator time constant
External/Status interrupt information
Write Register Functions
WRO
WRI
WR2
WR3
WR4
WRS
WR6
WR7
WR8
WR9
WR10
WRII
WR12
WRl3
WR14
WR1S
eRe initialize, initialization commands for the
various modes, shift right/shift left command
Transmit/Receive interrupt and data transfer mode
definition
Interrupt vector (accessed through either channel)
Receive parameters and control
TransmiUReceive miscellaneous parameters and
modes
Transmit parameters and controls
Sync characters or SDLC address field
Sync character or SDLC flag
Transmit buffer
Master interrupt control and reset (accessed
through either channel)
Miscellaneous transmitter/receiver control bits
Clock mode control
Lower byte of baud Fate generator time constant
Upper byte of baud rate generator time constant
Miscellaneous control bits
External/Status interrupt control
Table 1. Read and Write Register Functions
ignored. AD7 and AD6 are always ignored as
address bits and the register address itself
occupies AD4-ADl.
The system program first issues a series of
commands to initialize the basic mode of
operation. This is followed by other commands
to qualify conditions within the selected mode.
For example, the Asynchronous mode,
character length, clock rate, number of stop
bits, even or odd parity might be set first.
Then the Interrupt mode would be set, and
finally, receiver or transmitter enable.
641
11 Page | ||
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| PDF Descargar | [ Datasheet Z8030.PDF ] | |
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