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Descripción PCI/CardBus 10/100Mb/s Ethernet LAN Controller Hardware Reference Manual
Fabricantes Intel Corporation 
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No Preview Available ! 21143 Hoja de datos, Descripción, Manual

21143 PCI/CardBus 10/100Mb/s
Ethernet LAN Controller
Hardware Reference Manual
Revision 1.0
October 1998
Document Number: 278074-001

1 page




21143 pdf
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
Reset Commands ..........................................................................4-19
DMA Arbitration Scheme ...............................................................4-20
Interrupts ........................................................................................4-21
4.3.3.1 Receive and Transmit Interrupt Mitigation ........................4-22
Initialization Procedure...................................................................4-22
Receive Process ............................................................................4-23
4.3.5.1 Descriptor Acquisition .......................................................4-23
4.3.5.2 Frame Processing.............................................................4-23
4.3.5.3 Receive Process Suspended ............................................4-24
4.3.5.4 Receive Process State Transitions ...................................4-24
Transmit Process ...........................................................................4-25
4.3.6.1 Frame Processing.............................................................4-25
4.3.6.2 Transmit Polling Suspended .............................................4-25
4.3.6.3 Transmit Process State Transitions ..................................4-26
Card Information Structure.............................................................4-26
5 Host Bus Operation....................................................................................................5-1
5.1 Overview .......................................................................................................5-1
5.2 Bus Commands ............................................................................................5-1
5.3 Bus Slave Operation .....................................................................................5-2
5.3.1 Slave Read Cycle (I/O or Memory Target).......................................5-2
5.3.2 Slave Write Cycle (I/O or Memory Target) .......................................5-3
5.3.3 Configuration Read and Write Cycles..............................................5-4
5.4 Bus Master Operation ...................................................................................5-5
5.4.1 Bus Arbitration .................................................................................5-5
5.4.2 Memory Read Cycle .......................................................................5-6
5.4.3 Memory Write Cycle.........................................................................5-7
5.5 Termination Cycles .......................................................................................5-8
5.5.1 Slave-Initiated Termination ..............................................................5-8
5.5.1.1 Disconnect Termination ......................................................5-8
5.5.1.2 Retry Termination ...............................................................5-9
5.5.2 Master-Initiated Termination ..........................................................5-10
5.5.2.1 21143-Initiated Termination ..............................................5-10
5.5.2.2 Master Abort .....................................................................5-11
5.5.2.3 Memory-Controller-Initiated Termination ..........................5-11
5.5.2.4 Target Disconnect Termination .........................................5-12
5.6 Parity...........................................................................................................5-13
5.7 Parking........................................................................................................5-13
5.8 PCI/CardBus Clock Control through Clkrun................................................5-14
6 Network Interface Operation ......................................................................................6-1
6.1 MII/SYM Port.................................................................................................6-1
6.1.1 100BASE-T Terminology .................................................................6-1
6.1.2 Interface Description ........................................................................6-2
6.1.2.1 Signal Standards.................................................................6-2
6.1.2.2 Operating Modes ................................................................6-3
6.2 10BASE-T and AUI Functions ......................................................................6-4
6.2.1 Receivers and Drivers......................................................................6-4
6.2.2 Manchester Decoder........................................................................6-4
6.2.3 Manchester Encoder........................................................................6-4
6.2.4 Oscillator Circuitry............................................................................6-5
6.2.5 Smart Squelch .................................................................................6-5
6.2.6 Autopolarity Detector .......................................................................6-6
21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller Hardware Reference Manual
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21143 arduino
3-49 CSR1-PM Register Access Rules...............................................................3-31
3-50 Filter i Byte Mask Descriptions...................................................................3-32
3-51 Filter i Byte Mask Register Access Rules ...................................................3-32
3-52 Filter i Command Descriptions....................................................................3-33
3-53 Filter i Command Register Access Rules ...................................................3-33
3-54 Filter i Offset Descriptions...........................................................................3-34
3-55 Filter i Offset Register Access Rules ..........................................................3-34
3-56 Filter i CRC-16 Descriptions .......................................................................3-35
3-57 Filter i CRC-16 Register Access Rules .......................................................3-35
3-58 CSR2 Register Bit Field Description ...........................................................3-36
3-59 CSR2 Register Access Rules .....................................................................3-36
3-60 CSR2-PM Register Bit Field Description (Sheet 1 of 2)..............................3-37
3-61 CSR2-PM Register Access Rules...............................................................3-38
3-62 CSR3 Register Bit Fields Description .........................................................3-39
3-63 CSR3 Register Access Rules .....................................................................3-39
3-64 CSR4 Register Bit Fields Description .........................................................3-40
3-65 CSR4 Register Access Rules .....................................................................3-40
3-66 CSR5 Register Bit Fields Description (Sheet 1 of 2) ..................................3-42
3-67 Fatal Bus Error Bits.....................................................................................3-44
3-68 Transmit Process State...............................................................................3-44
3-69 Receive Process State................................................................................3-44
3-70 CSR5 Register Access Rules .....................................................................3-44
3-71 CSR6 Register Bit Fields Description (Sheet 1 of 3) ..................................3-46
3-72 Transmit Threshold .....................................................................................3-49
3-73 Port and Data Rate Selection .....................................................................3-49
3-74 Loopback Operation Mode..........................................................................3-49
3-75 Filtering Mode .............................................................................................3-50
3-76 CSR6 Register Access Rules .....................................................................3-50
3-77 CSR7 Register Bit Fields Description (Sheet 1 of 2) ..................................3-52
3-78 CSR7 Register Access Rules .....................................................................3-53
3-79 CSR8 Register Bit Fields Description .........................................................3-54
3-80 CSR8 Register Access Rules .....................................................................3-54
3-81 CSR9 Register Bit Fields Description (Sheet 1 of 2) ..................................3-55
3-82 CSR9 Register Access Rules .....................................................................3-56
3-83 CSR10 Register Bit Field Description .........................................................3-57
3-84 CSR10 Register Access Rules ...................................................................3-57
3-85 CSR11 Register Bit Fields Description ......................................................3-59
3-86 CSR11 Register Access Rules ...................................................................3-59
3-87 CSR12 Register Bit Fields Description (Sheet 1 of 2) ................................3-60
3-88 CSR12 Register Access Rules ...................................................................3-61
3-89 CSR13 Register Bit Fields Description .......................................................3-62
3-90 CSR13 Register Access Rules ...................................................................3-62
3-91 CSR14 Register Bit Fields Description (Sheet 1 of 3) ................................3-63
3-92 CSR14 Register Access Rules ...................................................................3-67
3-93 Twisted-Pair Compensation Behavior.........................................................3-67
3-94 CSR15 Register Bit Fields Description (Sheet 1 of 3) ................................3-69
3-95 CSR15 Register Access Rules ...................................................................3-71
3-96 Programming MII/SYM Operating Modes ...................................................3-72
3-97 Programming 10BASE-T, AUI, and BNC Operating Modes with
Autosensing Disabled and Autonegotiation Disabled ..............................................3-72
3-98 Programming 10BASE-T, AUI, and BNC Operating Modes with
21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller Hardware Reference Manual
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