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PDF GLT5160L16P-8TC Data sheet ( Hoja de datos )

Número de pieza GLT5160L16P-8TC
Descripción 16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM
Fabricantes ETC 
Logotipo ETC Logotipo



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No Preview Available ! GLT5160L16P-8TC Hoja de datos, Descripción, Manual

GLT5160L16
16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM
ADVANCED
FEATURES
u Single 3.3 V ±0.3 V power supply
u Clock frequency 100 MHz / 125 MHz / 143 MHz/
166 MHz
u Fully synchronous operation referenced to clock rising edge
u Dual bank operation controlled by BA (Bank Address)
u CAS latency- 2 / 3 (programmable)
u Burst length- 1 / 2 / 4 / 8 & Full Page (programmable)
u Burst type- sequential / interleave (programmable)
u Industrial grade available
GENERAL DESCRIPTION
The GLT5160L16 is a 2-bank x 524288-word x 16-bit Synchro-
nous DRAM, with LVTTL interface. All inputs and outputs are
referenced to the rising edge of CLK. The GLT5160L16 achieves
u Byte control by DQMU and DQML
u Column access - random
u Auto precharge / All bank precharge controlled by A[10]
u Auto refresh and Self refresh
u 4096 refresh cycles / 64 ms
u LVTTL Interface
u 400-mil, 50-Pin Thin Small Outline Package (TSOP II) with
0.8 mm lead pitch
u 60-Ball, 6.4mmx10.1mm VFBGA package with 0.65mm Ball
pitch & 0.35mm Ball diameter.
very high speed data rate up to 166 MHz, and is suitable for main
memory or graphic memory in computer systems.
DEC. 2003 (Rev.2.4) 1

1 page




GLT5160L16P-8TC pdf
Function Truth Table [1] [2] (Continued)
Current State
CS RAS CAS WE
READ with AUTO
PRECHARGE
H XX X
L HHH
L HH L
LH LH
L HL L
LL HH
L L HL
L LLH
L LLL
WRITE with AUTO
PRECHARGE
H X XX
LH HH
L HH L
L HLH
L HL L
LL HH
L LHL
L LLH
L LLL
PRE -CHARGING
HXX X
L HHH
L HHL
L HLX
L LH H
L LHL
L LLH
LL LL
ROW ACTIVATING
H XX X
L HH H
L HH L
L HLX
L LHH
L LHL
L LLH
L LLL
WRITE RECOVERING H X X X
L H HH
L HHL
L HLX
L L HH
L LHL
L L LH
L LLL
Address [3]
X
X
X
BA, CA, A[10]
BA, CA, A[10]
BA, RA
BA, A[10]
X
Op-Code, Mode-Add
X
X
X
BA, CA, A[10]
BA, CA, A[10]
BA, RA
BA, A[10]
X
Op-Code, Mode-Add
X
X
X
BA, CA, A[10]
BA, RA
BA, A[10]
X
Op-Code, Mode-Add
X
X
X
BA, CA, A[10]
BA, RA
BA, A[10]
X
Op-Code, Mode-Add
X
X
X
BA, CA, A[10]
BA, RA
BA, A[10]
X
Op-Code, Mode-Add
Command
DESEL
NOP
TBST
READ / READA
WRITE / WRITEA
ACT
PRE / PREA
REFA
MRS
DESEL
NOP
TBST
READ / READA
WRITE / WRITEA
ACT
PRE / PREA
REFA
MRS
DESEL
NOP
TBST
READ / WRITE
ACT
PRE / PREA
REFA
MRS
DESEL
NOP
TBST
READ / WRITE
ACT
PRE / PREA
REFA
MRS
DESEL
NOP
TBST
READ / WRITE
ACT
PRE / PREA
REFA
MRS
Action [4]
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
ILLEGAL
ILLEGAL
Bank Active / ILLEGAL [5]
ILLEGAL [5]
ILLEGAL
ILLEGAL
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
ILLEGAL
ILLEGAL
Bank Active / ILLEGAL [5]
ILLEGAL [5]
ILLEGAL
ILLEGAL
NOP (Idle after tRP)
NOP (Idle after tRP)
ILLEGAL [5]
ILLEGAL [5]
ILLEGAL [5]
NOP [6] (Idle after tRP)
ILLEGAL
ILLEGAL
NOP (Row Active after tRCD)
NOP (Row Active after tRCD)
ILLEGAL [5]
ILLEGAL [5]
ILLEGAL [5]
ILLEGAL [5]
ILLEGAL
ILLEGAL
NOP
NOP
ILLEGAL [5]
ILLEGAL [5]
ILLEGAL [5]
ILLEGAL [5]
ILLEGAL
ILLEGAL
G-LINK Technology
DEC. 2003 (Rev.2.4)
5

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GLT5160L16P-8TC arduino
Read
After tRCD from the bank activation, a READ command can be
issued. 1st output data is available after the CAS Latency from the
READ, followed by (BL-1) consecutive data when the Burst Length
is BL. The start address is specified by A[7:0], and the address
sequence of burst data is defined by the Burst Type. A READ com-
mand may be applied to any active bank, so the row precharge time
(tRP) can be hidden behind continuous output data (in case of BL =
4) by interleaving the dual banks. When A[10] is high at a READ
command, the auto-precharge (READA) is performed. Any com-
mand (READ, WRITE, PRE, ACT) to the same bank is inhibited till
the internal precharge is complete. The internal precharge start tim-
ing depends on CAS Latency. The next ACT command can be
issued after tRP from the internal precharge timing.
CLK
Command
A[9:0]
A[10]
BA
DQ
ACT
Xa
tRCD
REA
Ya
ACT
Xb
REA
Yb
PRE
Xa 0 Xb 0 0
0 01 10
Burst Length
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
CAS Latency
Figure 4. Dual Bank Interleaving READ (BL=4, CL=3)
CLK
Command
A[9:0]
A[10]
BA
DQ
ACT
Xa
tRCD
READ A
Y
ACT
tRP
Xa
Xa 1
Xa
00
0
Qa0 Qa1 Qa2 Qa3
Internal Precharge begins
Figure 5. READ with Auto-Precharge (BL=4, CL=3)
CLK
Command
CL=3 DQ
CL=2 DQ
ACT
READ A
Qa0 Qa1 Qa2 Qa3
Qa0 Qa1 Qa2
Qa3
Internal Precharge Start Timing
Figure 6. READ Auto-Precharge Timing (BL=4)
G-LINK Technology
DEC. 2003 (Rev.2.4)
11

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