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PDF KM62256CL-L Data sheet ( Hoja de datos )

Número de pieza KM62256CL-L
Descripción 32K x 8 bit Low Power CMOS Static RAM
Fabricantes Samsung 
Logotipo Samsung Logotipo



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No Preview Available ! KM62256CL-L Hoja de datos, Descripción, Manual

KM62256C Family
Document Title
32Kx8 bit Low Power CMOS Static RAM
CMOS SRAM
Revision History
Revision No History
0.0 Advance information
0.1 Initial draft
1.0 Finalize
2.0 Revise
- Add 45ns part with 30pF test load
3.0 Revise
- Change specification format and merge :
Commercial, Extended, Industrial product in same datasheets.
4.0 Revise
- Change Speed bin
Erase 45ns part from commercial product and 100ns from
extended and industrial product.
- Production change
Erase Low power product from TSOP package
Draft Data
February 12th 1993
Remark
Design target
November 2nd 1993 Preliminary
September 24th 1994 Final
August 12th 1995
Final
April 15th 1996
Final
December 19 1997 Final
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications and product. SAMSUNG Electronics will evaluate and reply to your requests and questions about
device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
1 Revision 4.0
December 1997

1 page




KM62256CL-L pdf
KM62256C Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falingl time : 5ns
input and output reference voltage : 1.5V
Output load (See right) :CL=100pF+1TTL
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS(Vcc=4.5~5.5V, KM62256C Family : TA=0 to 70°C, KM62256CE Family : TA=-25 to 85°C,
KM62256CI Family : TA=-40 to 85°C)
Parameter List
Read
Write
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
Symbol
tRC
tAA
tCO
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
Speed Bins
55ns
70ns
Min Max Min Max
55 - 70 -
- 55 - 70
- 55 - 70
- 25 - 35
10 - 10 -
5- 5 -
0 20 0 30
0 20 0 30
5- 5 -
55 - 70 -
45 - 60 -
0- 0 -
45 - 60 -
40 - 50 -
0- 0 -
0 20 0 25
25 - 30 -
0- 0 -
5- 5 -
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
VDR
KM62256CL
KM62256CL-L
IDR KM62256CLE
KM62256CLE-L
KM62256CLI
KM62256CLI-L
tSDR
tRDR
Test Condition
CSVcc-0.2V
Vcc=3.0V
CSVcc-0.2V
L-Ver
LL-Ver
L-Ver
LL-Ver
L-Ver
LL-Ver
See data retention waveform
Min Typ Max Unit
2.0 - 5.5 V
- 1 50
- 0.5 10
- - 50 µA
- - 25
- - 50
- - 25
0--
ms
5--
5 Revision 4.0
December 1997

5 Page










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