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PDF NCP51200 Data sheet ( Hoja de datos )

Número de pieza NCP51200
Descripción 3 Amp Termination Regulator
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No Preview Available ! NCP51200 Hoja de datos, Descripción, Manual

NCP51200, NCV51200
3 Amp VTT Termination
Regulator DDR1, DDR2,
DDR3, LPDDR3, DDR4
The NCP51200 is a source/sink Double Data Rate (DDR)
termination regulator specifically designed for low input voltage and
low−noise systems where space is a key consideration.
The NCP51200 maintains a fast transient response and only requires
a minimum output capacitance of 20 mF. The NCP51200 supports a
remote sensing function and all power requirements for DDR VTT bus
termination. The NCP51200 can also be used in low−power chipsets
and graphics processor cores that require dynamically adjustable
output voltages.
The NCP51200 is available in the thermally−efficient DFN10
Exposed Pad package, and is rated both Green and Pb−free.
Features
For Automotive Applications
Input Voltage Rails: Supports 2.5 V, 3.3 V and 5 V Rails
PVCC Voltage Range: 1.1 to 3.5 V
Integrated Power MOSFETs
Fast Load−Transient Response
PGOOD − Logic output pin to Monitor VTT Regulation
EN − Logic input pin for Shutdown mode
VRI − Reference Input Allows for Flexible Input Tracking Either
Directly or Through Resistor Divider
Remote Sensing (VTTS)
Built−in Soft Start, Under Voltage Lockout and Over Current Limit
Thermal Shutdown
Small, Low−Profile 10−pin, 3x3 DFN Package
NCV51200MWTXG − Wettable Flank Option for Enhanced Optical
Inspection
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable*
These Devices are Pb−Free and are RoHS Compliant
Applications
DDR Memory Termination
Desktop PC’s, Notebooks, and Workstations
Servers and Networking equipment
Telecom/Datacom, GSM Base Station
Graphics Processor Core Supplies
Set Top Boxes, LCD−TV/PDP−TV, Copier/Printers
Chipset/RAM Supplies as Low as 0.5 V
Active Bus Termination
www.onsemi.com
DFN10, 3x3, 0.5P
CASE 485C
MARKING DIAGRAM
51200
ALYWG
G
51200 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTION
VRI
PVCC
VTT
PGND
VTTS
+
1
2
3
4
5
GND
10 VCC
9 PGOOD
8 GND
7 EN
6 VRO
Exposed Pad
ORDERING INFORMATION
Device
NCP51200MNTXG
Package
DFN10
(Pb−Free)
Shipping
3000 / Tape &
Reel
NCV51200MNTXG* DFN10 3000 / Tape &
(Pb−Free)
Reel
NCV51200MWTXG* DFN10 3000 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 6
1
Publication Order Number:
NCP51200/D

1 page




NCP51200 pdf
NCP51200, NCV51200
Figure 2. Block Diagram
www.onsemi.com
5

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