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Número de pieza R5F571MJDDLJ
Descripción 240-MHz 32-bit RX MCU
Fabricantes Renesas 
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Features
Datasheet
RX71M Group
Renesas MCUs
R01DS0249EJ0100
Rev.1.00
240-MHz 32-bit RX MCU, on-chip FPU, 480 DMIPS, up to 4-MB flash memory,
Jan 15, 2015
512-KB SRAM, various communications interfaces including IEEE 1588-compliant Ethernet MAC,
high-speed USB 2.0 with battery charging, SD host interface (optional), quad SPI, and CAN, 12-bit A/D
converter, RTC, encryption (optional), serial interface for audio, CMOS camera interface
Features
32-bit RXv2 CPU core
Max. operating frequency: 240 MHz
Capable of 480 DMIPS in operation at 240 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories
and between registers)
32-bit multiplier (fastest instruction execution takes one CPU clock
cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
JTAG and FINE (one-line) debugging interfaces
Low-power design and architecture
Operation from a single 2.7- to 3.6-V supply
Low power consumption: A product that supports all peripheral
functions draws only 0.2mA/MHz (Typ.).
RTC is capable of operation from a dedicated power supply.
Four low-power modes
On-chip code flash memory
Supports versions with up to 4 Mbytes of ROM
No wait states at up to 120 MHz or when the AFU is hit, one wait
state at above 120 MHz and when the AFU is missed
User code is programmable by on-board or off-board programming.
Programming/erasing as background operations (BGOs)
On-chip data flash memory
64 Kbytes, reprogrammable up to 100,000 times
Programming/erasing as background operations (BGOs)
On-chip SRAM
512 Kbytes of SRAM (no wait states except in the 256 Kbytes from
0004 0000h to 0007 FFFFh when ICLK is set to 120 MHz or faster)
32 Kbytes of RAM with ECC (single-error correction and double
error detection)
8 Kbytes of standby RAM (backup on deep software standby)
Data transfer
DMAC: 8 channels
DTC
EXDMAC: 2 channels
DMAC for the Ethernet controller: 3 channels for 176- and 177-pin
products; 2 channels for 100-, 144-, and 145-pin products
Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
External crystal oscillator or internal PLL for operation at 8 to 24
MHz
Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20
MHz
120-kHz clock for the IWDTa
Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Real-time clock counting and binary counting modes are selectable
Time capture function
(for capturing times in response to event-signal input)
Independent watchdog timer
120-kHz (1/2 LOCO frequency) clock operation
Useful functions for IEC60730 compliance
Oscillation-stoppage detection, frequency measurement, CRC,
IWDTa, self-diagnostic function for the A/D converter, etc.
Register write protection function can protect values in important
registers against overwriting.
PLQP0176KB-A 24 × 24 mm, 0.5-mm pitch
PLQP0144KA-A 20 × 20 mm, 0.5-mm pitch
PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch
PTLG0177KA-A 8 × 8 mm, 0.5-mm pitch
PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch
PTLG0100JA-A 7 × 7 mm, 0.65-mm pitch
PLBG0176GA-A 13 × 13mm, 0.8-mm pitch
Various communications interfaces
IEEE 1588-compliant Ethernet MAC
(for 176- and 177-pin products: 2 modules)
PHY layer for host/function or OTG controller (1) with high-speed
USB 2.0 with battery charging transfer (only for 176- and 177-pin
products)
PHY layer (1) for host/function or OTG controller (1) with full-
speed USB 2.0 transfer
CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up
to 3 modules)
SCIg and SCIh with multiple functionalities (up to 9)
Choose from among asynchronous mode, clock-synchronous mode,
smart-card interface mode, simplified SPI, simplified I2C, and
extended serial mode.
SCIFA with 16-byte transmission and reception FIFOs (up to 4
interfaces)
I2C bus interface for transfer at up to 1 Mbps (up to 2 interfaces)
Four-wire QSPI (1 interface) in addition to RSPIa (2 interfaces)
Parallel data capture unit (PDC) for the CMOS camera interface (not
in 100-pin products)
SD host interface (optional: 1 interface) with a 1- or 4-bit SD bus for
use with SD memory or SDIO
MMCIF with 1-, 4-, or 8-bit transfer bus width
External address space
Buses for full-speed data transfer (max. operating frequency of 60
MHz)
8 CS areas
8-, 16-, or 32-bit bus space is selectable per area
Independent SDRAM area (128 Mbytes)
Up to 29 extended-function timers
16-bit TPUa, MTU3a, and GPTa: input capture, output compare,
PWM waveform output
8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2
channels)
12-bit A/D converter
Two 12-bit units (8 channels for unit 0; 21 channels for unit 1)
Self diagnosis
Detection of analog input disconnection
12-bit D/A converter: 2 channels
On-chip operational amplifier output or direct input selectable
Temperature sensor for measuring temperature
within the chip
Encryption (optional)
AES (key lengths: 128, 196, and 256 bits)
DES (key lengths: 56 bits (DES); 3 × 56 bits (T-DES))
SHA (SHA-1 (128), SHA-2 (224 or 256), HMAC (160, 224, or 256))
Up to 127 pins for general I/O ports
5-V tolerance, open drain, input pull-up, switchable driving ability
Operating temp. range
–40C to +85C
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 1 of 228

1 page




R5F571MJDDLJ pdf
RX71M Group
1. Overview
Table 1.1
Outline of Specifications (4/10)
Classification Module/Function
Event link controller (ELC)
Timers
16-bit timer pulse unit
(TPUa)
Timers
Multifunction timer
pulse unit (MTU3a)
Port output enable 3
(POE3a)
Description
Event signals such as interrupt request signals can be interlinked with the operation of
functions such as timer counting, eliminating the need for intervention by the CPU to
control the functions.
119 internal event signals can be freely combined for interlinked operation with
connected functions.
Event signals from peripheral modules can be used to change the states of output pins
(of ports B and E).
Changes in the states of pins (of ports B and E) being used as inputs can be interlinked
with the operation of peripheral modules.
(16 bits × 6 channels) × 1 unit
Maximum of 16 pulse-input/output possible
Select from among seven or eight counter-input clock signals for each channel
Input capture/output compare function
Output of PWM waveforms in up to 15 phases in PWM mode
Support for buffered operation, phase-counting mode (two phase encoder input) and
cascade-connected operation (32 bits × 2 channels) depending on the channel.
PPG output trigger can be generated
Capable of generating conversion start triggers for the A/D converters
Digital filtering of signals from the input capture pins
Event linking by the ELC
9 channels (16 bits × 8 channels, 32 bits × 1 channel)
Maximum of 16 pulse-input/output and 3 pulse-input possible
Select from among 13 counter-input clock signals for each channel (PCLKA/1, PCLKA/
2, PCLKA/4, PCLKA/8, PCLKA/16, PCLK/A32, PCLKA/64, PCLKA/256, PCLKA/1024,
MTCLKA, MTCLKB, MTCLKC, MTCLKD)
11 of the signals are available for channels 1, 3 and 4, 12 are available for channel 2,
and 9 are available for channels 5 to 8.
Input capture function
39 output compare/input capture registers
Counter clear operation (synchronous clearing by compare match/input capture)
Simultaneous writing to multiple timer counters (TCNT)
Simultaneous register input/output by synchronous counter operation
Buffered operation
Support for cascade-connected operation
43 interrupt sources
Automatic transfer of register data
Pulse output mode
Toggle/PWM/complementary PWM/reset-synchronized PWM
Complementary PWM output mode
Outputs non-overlapping waveforms for controlling 3-phase inverters
Automatic specification of dead times
PWM duty cycle: Selectable as any value from 0% to 100%
Delay can be applied to requests for A/D conversion.
Non-generation of interrupt requests at peak or trough values of counters can be
selected.
Double buffer configuration
Reset synchronous PWM mode
Three phases of positive and negative PWM waveforms can be output with desired duty
cycles.
Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2)
Counter functionality for dead-time compensation
Generation of triggers for A/D converter conversion
A/D converter start triggers can be skipped
Digital filter function for signals on the input capture and external counter clock pins
PPG output trigger can be generated
Event linking by the ELC
Control of the high-impedance state of the MTU3/GPT's waveform output pins
5 pins for input from signal sources: POE0, POE4, POE8, POE10, POE11
Initiation on detection of short-circuited outputs (detection of simultaneous PWM output
to the active level)
Initiation by oscillation-stoppage detection or software
Additional programming of output control target pins is enabled
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 5 of 228

5 Page





R5F571MJDDLJ arduino
RX71M Group
Table 1.1
Outline of Specifications (10/10)
Classification Module/Function
Description
On-chip debugging system
E1 emulator (JTAG and FINE interfaces)
E20 emulator (JTAG interface)
Note 1. Magic PacketTM is a registered trademark of Advanced Micro Devices, Inc.
Note 2. Setting is only possible when the input sampling rate 44.1 kHz is selected.
Note 3. The product part number differs according to whether or not it supports encryption.
Note 4. The product part number differs according to whether or not it includes an SDHI (SD host interface).
1. Overview
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 11 of 228

11 Page







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