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PDF L6995DTR Data sheet ( Hoja de datos )
| Número de pieza | L6995DTR | |
| Descripción | STEP DOWN CONTROLLER FOR HIGH DIFFERENTIAL INPUT-OUTPUT CONVERSION | |
| Fabricantes | STMicroelectronics | |
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L6995
STEP DOWN CONTROLLER FOR HIGH DIFFERENTIAL
INPUT-OUTPUT CONVERSION
FEATURE
s CONSTANT ON TIME TOPOLOGY ALLOWS
OPERATION WITH LOWER DUTY THAN
PWM TOPOLOGY
s VERY FAST LOAD TRANSIENTS
s 5V Vcc SUPPLY
s 1.5V TO 28V INPUT VOLTAGE RANGE
s 0.9V ±1% VREF
s MINIMUM OUTPUT VOLTAGE AS LOW AS 0.9V
s SELECTABLE SINKING MODE
s LOSSLESS CURRENT LIMIT
s REMOTE SENSING
s OVP,UVP LATCHED PROTECTIONS
s 600µA TYP QUIESCENT CURRENT
s POWER GOOD AND OVP SIGNALS
s PULSE SKIPPING AT LIGHT LOADS
APPLICATIONS
s I/O BUS FOR CPU CORE SUPPLY
s NOTEBOOK COMPUTERS
s NETWORKING DC-DC
s DISTRIBUTED POWER
TSSOP20
ORDERING NUMBERS: L6995D
L6995DTR
DESCRIPTION
The device is a step-down controller specifically de-
signed to provide extremely high efficiency conver-
sion, with losses current sensing tecnique.
The "constant on-time" topology assures fast load
transient response. The embedded "voltage feed-for-
ward" provides nearly constant switching frequency
operation.
An integrator can be introduced in the control loop to
reduce the static output voltage error.
The available remote sensing improve the static and
dynamic regulation recovering the wires voltage
drop. Pulse skipping technique reduces power con-
sumption at light load. Drivers current capability al-
lows output current in excess of 20A.
MINIMUM COMPONENT COUNT APPLICATION
28V
Rin2
Rin1
5V
OSC
BOOT
HGATE
HS
CIN
D
C BOOT
BOOT
5V
Vo
PHASE
RILIM
LGATE
ILIM PGND
L6995 GND
NOSKIP
VSENSE
LS
DS
L
COUT
0.9V
CSS
SS
INT
VFB
VREF
CVREF
December 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
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1 page  
Figure 1. Functional & Block Diagram
L6995
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5 Page 
L6995
1.6 Protection and fault
Sensing VSENSE pin voltage performs output protection. The nature of the fault (that is, latched OV or latched
UV) is given by the PGOOD and OVP pins. If the output voltage is between the 89% (typ.) and 110% (typ) of
the regulated value, PGOOD is high. If a hard overvoltage or an undervoltage occurs, the device is latched: low
side MOSFET is turned on, high side MOSFET is turned off and PGOOD goes low. In case the system detects
an overvoltage the OVP pin goes high.
To recover the functionality the device must be shut down and restarted thought the SHDN pin, or the supply
has to be removed, and restart with the correct sequence.
These features are useful to protect against short-circuit (UV fault) as well as high side MOSFET short (OV
fault).
1.7 Drivers
The integrated high-current drivers allow using different size of power MOSFET, maintaining fast switching tran-
sition. The driver for the high side MOSFET uses the BOOT pin for supply and PHASE pin for return (floating
driver). The driver for the low side MOSFET uses the VDR pin for the supply and PGND pin for the return. The
main feature is the adaptive anti-cross-conduction protection, which prevents from both high side and low side
MOSFET to be on at the same time, avoiding a high current to flow from VIN to GND. When high side MOSFET
is turned off the voltage on the pin PHASE begins to fall; the low side MOSFET is turned on only when the volt-
age on PHASE pin reaches 250mV. When low side is turned off, high side remains off until LGATE pin voltage
reaches 500mV. This is important since the driver can work properly with a large range of external power MOS-
FETS.
The current necessary to switch the external MOSFETS flows through the device, and it is proportional to the
MOSFET gate charge and the switching frequency. So the power dissipation of the device is function of the ex-
ternal power MOSFET gate charge and switching frequency.
Eq 14 Pd rive r = Vcc ⋅ Qg TOT ⋅ FSW
The maximum gate charge values for the low side and high side are given from:
Eq 15
QMAXHS =
f--S----W-----0-
fSW
⋅
75 n C
Eq 16
QMAXLS
=
f--S----W-----0-
fSW
⋅
125 n C
Where fSW0 = 500Khz. The equations above are valid for TJ = 150°C. If the system temperature is lower the QG
can be higher.
For the Low Side driver the max output gate charge meets another limit due to the internal traces degradation;
in this case the maximum value is QMAXLS = 125nC.
The low side driver has been designed to have a low resistance pull-down transistor, around 0.5 ohms. This
prevents the voltage on LGATE pin raises during the fast rise-time of the pin PHASE, due to the Miller effect.
2 APPLICATION INFORMATION
2.1 20A Demo board description
The demoboard shows the device operation in general purpose applications. The evaluation board allows using
only one supply because the on board linear regulator LM317LD; the linear regulator supplies the device
through the J1. Output current in excess of 20A can be reached dependently on the MOSFET type. The SW1
is used to start the device (when the supplies are already present) and to select the PFM/PWM mode.
11/25
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