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PDF FXMA2102 Data sheet ( Hoja de datos )

Número de pieza FXMA2102
Descripción 2-Bit Voltage Translator / Buffer / Repeater / Isolator
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FXMA2102 Hoja de datos, Descripción, Manual

August 2012
FXMA2102
Dual Supply, 2-Bit Voltage Translator / Buffer /
Repeater / Isolator for I2C Applications
Features
Bi-Directional Interface between Any Two Levels:
1.65 V to 5.5 V
Direction Control not Needed
System GPIO Resources Not Required when OE
Tied to VCCA
I2C 400 pF Buffer / Repeater
I2C Bus Isolation
A/B Port VOL = 175 mV (Typical), VIL = 150 mV,
IOL = 6 mA
Open-Drain Inputs / Outputs
Accommodates Standard-Mode and Fast-Mode
I2C-Bus Devices
Supports I2C Clock Stretching & Multi-Master
Fully Configurable: Inputs and Outputs Track VCC
Control Input (/OE) Referenced to VCCA.
Non-Preferential Power-Up; Either VCC May Be
Powered-Up First
Outputs Switch to 3-State if Either VCC is at GND
Tolerant Output Enable: 5 V
Packaged in 8-Terminal Leadless MicroPak™
(1.6 mm x 1.6 mm) and Ultrathin MLP
(1.2 mm x 1.4 mm)
ESD Protection Exceeds:
- 8 kV HBM ESD (per JESD22-A114)
- 2 kV CDM (per JESD22-C101)
Description
The FXMA2102 is a high-performance configurable
dual-voltage-supply translator for bi-directional voltage
translation over a wide range of input and output
voltages levels.
Intended for use as a voltage translator between I2C-
Bus® complaint masters and slaves.
The device is designed so that the A port tracks the
VCCA level and the B port tracks the VCCB level. This
allows for bi-directional A/B port voltage translation
between any two levels from 1.65 V to 5.5 V. VCCA can
equal VCCB from 1.65V to 5.5V. The OE pin is
referenced to VCCA.
Either VCC can be powered-up first. Internal power-down
control circuits place the device in 3-state if either VCC is
removed.
The two ports of the device have automatic direction
sense capability. Either port may sense an input signal
and transfer it as an output signal to the other port.
Ordering Information
Part Number
FXMA2102L8X
FXMA2102UMX
Operating
Temperature Range
-40 to +85°C
Top
Mark
XN
Package
8-Lead MicroPak™, 1.6 mm Wide
8-Lead Ultrathin MLP, 1.2 mm x 1.4 mm
Packing
Method
5000 Units on
Tape and Reel
© 2010 Fairchild Semiconductor Corporation
FXMA2102 • Rev. 1.0.5
www.fairchildsemi.com

1 page




FXMA2102 pdf
Functional Description
Power-Up/Power-Down Sequencing
FXM translators offer an advantage in that either VCC
may be powered up first. This benefit derives from the
chip design. When either VCC is at 0 V, outputs are in a
high-impedance state. The control input (OE) is
designed to track the VCCA supply. A pull-down resistor
tying OE to GND should be used to ensure that bus
contention, excessive currents, or oscillations do not
occur during power-up/power-down. The size of the pull-
down resistor is based upon the current-sinking
capability of the device driving the OE pin.
The recommended power-up sequence is:
1. Apply power to the first VCC.
2. Apply power to the second VCC.
3. Drive the OE input HIGH to enable the device.
The recommended power-down sequence is:
1. Drive OE input LOW to disable the device.
2. Remove power from either VCC.
3. Remove power from other VCC.
Note:
4. Alternatively, the OE pin can be hardwired to VCCA
to save GPIO pins. If OE is hardwired to VCCA,
either VCC can be powered up or down first.
Application Circuit
© 2010 Fairchild Semiconductor Corporation
FXMA2102 • Rev. 1.0.5
Figure 4. Application Circuit
5
www.fairchildsemi.com

5 Page





FXMA2102 arduino
AC Characteristics
Output Load: CL = 50 pF, RPU = 2.2 kΩ, and TA = -40°C to +85°C.
Symbol
Parameter
VCCB
4.5 to 5.5 V 3.0 to 3.6 V 2.3 to 2.7 V 1.65 to 1.95 V Unit
Typ. Max. Typ. Max. Typ. Max. Typ. Max.
VCCA = 4.5 to 5.5 V
tPLH
A to B
B to A
1
1
3
3
1
2
3
4
1
3
3
5
1
4
3
7
ns
tPHL
A to B
B to A
2
2
4
4
3
2
5
5
4
2
6
6
5
5
7
7
ns
tPZL
OE to A
OE to B
4
3
5
5
6 10 5
475
9
8
7 15
10 15
ns
tPLZ
tskew
OE to A
OE to B
A Port, B Port(14)
65 100 65 105 65 105 65 105
5 9 6 10 7 12 9 16
0.50 1.50 0.50 1.00 0.50 1.00 0.50 1.00
ns
ns
VCCA = 3.0 to 3.6 V
tPLH
A to B
B to A
2.0 5.0 1.5 3.0 1.5 3.0 1.5 3.0
1.5 3.0 1.5 4.0 2.0 6.0 3.0 9.0
ns
tPHL
A to B
B to A
2.0 4.0 2.0 4.0 2.0 5.0 3.0 5.0
2.0 4.0 2.0 4.0 2.0 5.0 3.0 5.0
ns
tPZL
OE to A
OE to B
4.0
4.0
8.0
8.0
5.0
6.0
9.0
9.0
6.0 11.0 7.0 15.0
8.0 11.0 10.0 14.0
ns
tPLZ
tskew
OE to A
OE to B
A Port, B Port(14)
100 115 100 115 100 115 100 115
5 10 4 8 5 10 9 15
0.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0
ns
ns
VCCA = 2.3 to 2.7 V
tPLH
A to B
B to A
2.5
1.5
5.0
3.0
2.5
2.0
5.0
4.0
2.0
3.0
4.0
6.0
1.0 3.0
5.0 10.0
ns
tPHL
A to B
B to A
2.0 5.0 2.0 5.0 2.0 5.0 3.0 6.0
2.0 5.0 2.0 5.0 2.0 5.0 3.0 6.0
ns
tPZL
OE to A
OE to B
5.0 10.0 5.0 10.0 6.0 12.0 9.0 18.0
4.0 8.0 4.5 9.0 5.0 10.0 9.0 18.0
ns
tPLZ
tskew
OE to A
OE to B
A Port, B Port(14)
100 115 100 115 100 115 100 115
65 110 65 110 65 115 12
25
0.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0
ns
ns
VCCA = 1.65 to 1.95 V
tPLH
A to B
B to A
4
1.0
7
2.0
4
1.0
7
2.0
5
1.5
8
3.0
5 10
5.0 10.0
ns
tPHL
A to B
B to A
5
4
8
8
3
3
7
7
3
3
7
7
3
3
7
7
ns
tPZL
OE to A
OE to B
11 15
6 14
11 14 14 28 14
6 12 6 12 9
23
16
ns
tPLZ
tskew
OE to A
OE to B
A Port, B Port(14)
75 115 75 115 75 115 75 115
75 115 75 115 75 115 75 115
0.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0
ns
ns
Note:
14. Skew is the variation of propagation delay between output signals and applies only to output signals on the same
port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 15). Skew is
guaranteed, but not tested.
© 2010 Fairchild Semiconductor Corporation
FXMA2102 • Rev. 1.0.5
11
www.fairchildsemi.com

11 Page







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