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PDF M48T37V Data sheet ( Hoja de datos )

Número de pieza M48T37V
Descripción 256 Kbit (32 Kbit x 8) TIMEKEEPER SRAM
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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M48T37Y
M48T37V
5.0 or 3.3 V, 256 Kbit (32 Kbit x 8) TIMEKEEPER® SRAM
Features
Integrated ultra low power SRAM, real-time
clock, power-fail control circuit, and battery
Frequency test output for real-time clock
software calibration
Automatic power-fail chip deselect and WRITE
protection
Watchdog timer
WRITE protect voltage
(VPFD = Power-fail deselect voltage):
– M48T37Y: VCC = 4.5 to 5.5 V
4.2 V VPFD 4.5 V
– M48T37V: VCC = 3.0 to 3.6 V
2.7 V VPFD 3.0 V
Packaging includes a 44-lead SOIC and
SNAPHAT® top (to be ordered separately)
SOIC package provides direct connection for a
SNAPHAT® top which contains the battery and
crystal
Microprocessor power-on reset (valid even
during battery backup mode)
Programmable alarm output active in the
battery backup mode
Battery low flag
RoHS compliant
– Lead-free second level interconnect
SNAPHAT® (SH)
Battery/crystal
44
1
SOH44 (MH)
44-pin SOIC
August 2010
Doc ID 7019 Rev 9
1/30
www.st.com
1

1 page




M48T37V pdf
M48T37Y, M48T37V
1 Description
Description
Caution:
The M48T37Y/V TIMEKEEPER® RAM is a 32 Kb x 8 non-volatile static RAM and real-time
clock. The monolithic chip is available in a special package which provides a highly
integrated battery-backed memory and real-time clock solution.
The 44-lead, 330 mil SOIC package provides sockets with gold-plated contacts at both ends
for direct connection to a separate SNAPHAT housing containing the battery and crystal.
The unique design allows the SNAPHAT® battery/crystal package to be mounted on top of
the SOIC package after the completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal
damage due to the high temperatures required for device surface-mounting. The SNAPHAT
housing is keyed to prevent reverse insertion.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in tape
& reel form. For the 44-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part
number is “M4T28-BR12SH” or “M4T32-BR12SH”.
Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the
lithium button-cell battery.
Figure 1. Logic diagram
VCC
15
A0-A14
8
DQ0-DQ7
W M48T37Y RST
E M48T37V IRQ/FT
G
WDI
VSS
AI02172
Doc ID 7019 Rev 9
5/30

5 Page





M48T37V arduino
M48T37Y, M48T37V
Operation modes
Table 4. WRITE mode AC characteristics
Symbol
Parameter(1)
M48T37Y
–70
M48T37V
–100
Unit
Min Max Min Max
tAVAV
tAVWL
tAVEL
tWLWH
tELEH
tWHAX
tEHAX
tDVWH
tDVEH
tWHDX
tEHDX
tWLQZ(2)(3)
tAVWH
WRITE cycle time
Address valid to WRITE enable low
Address valid to chip enable low
WRITE enable pulse width
Chip enable low to chip enable high
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
Input valid to chip enable high
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
70
0
0
50
55
0
0
30
30
5
5
60
100
0
0
80
80
10
10
50
50
5
5
25 50
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVEH Address valid to chip enable high
60
80
ns
tWHQX(2)(3) WRITE enable high to output transition
5
10 ns
1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V
(except where noted).
2. CL = 5 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Note:
Data retention mode
With valid VCC applied, the M48T37Y/V operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “Don't care.”
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF.
The M48T37Y/V may respond to transient noise spikes on VCC that reach into the deselect
window during the time the device is sampling VCC. Therefore, decoupling of the power
supply lines is recommended. When VCC drops below VSO, the control circuit switches
power to the internal battery which preserves data and powers the clock. The internal button
cell will maintain data in the M48T37Y/V for an accumulated period of at least 7 years at
room temperature when VCC is less than VSO. As system power returns and VCC rises
above VSO, the battery is disconnected and the power supply is switched to external VCC.
Normal RAM operation can resume tREC after VCC reaches VPFD (max).
For more information on battery storage life refer to the application note AN1012.
Doc ID 7019 Rev 9
11/30

11 Page







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