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PDF GS88019AT Data sheet ( Hoja de datos )
| Número de pieza | GS88019AT | |
| Descripción | 9Mb Sync Burst SRAMs | |
| Fabricantes | GSI Technology | |
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Datasheet Errata
Revision: 5/17/02
GS88019/33/37AT
Base datasheet:
GS88019/33/37AT, Rev.1.00, 3/2002
Product(s) covered in this supplement:
GS88019/33/37AT-250/225/200/166/150/133
Product specification(s) addressed by this supplement:
Pin 14
Note: The specifications cited in the base datasheet for the products addressed by this errata remain in force except where
superseded by the information in this errata.
1/5
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1 page  
Datasheet Errata
Revision: 5/17/02
GS88019/33/37AT
TQFP Pin Description
Pin Location
37, 36
35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46,
47, 48, 49, 50, 43
80
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
18, 19, 22, 23, 24, 25, 28, 29
51, 80, 1, 30
14, 16, 38, 39, 42, 66
51, 80, 1, 30
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57
75, 78, 79,
1, 2, 3, 6, 7,
25, 28, 29, 30, 95, 96, 42
87
93, 94
Symbol
A0, A1
A2–A17
A18
DQA1–DQA8
DQB1–DQB8
DQC1–DQC8
DQD1–DQD8
DQA9, DQB9,
DQC9, DQD9
NC
NC
DQA1–DQA9
DQB1–DQB9
NC
BW
BA, BB
95, 96
BC, BD
89
88
98, 92
97
86
83
84, 85
64
31
15, 41, 65, 91
5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
CK
GW
E1, E3
E2
G
ADV
ADSP, ADSC
ZZ
LBO
VDD
VSS
VDDQ
Type
I
I
I
I/O
I/O
—
—
I/O
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
14
VDDQ/DNU
—
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Address Inputs (x18 versions)
Data Input and Output pins (x32, x36 Version)
Data Input and Output pins (x36 Version)
No Connect (x32, x36 Version)
No Connect (x32 Version)
Data Input and Output pins (x18 Version)
No Connect (x18 Version)
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Byte Write Enable for DQC, DQD Data I/Os; active low
(x32, x36 Version)
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
VDDQ or VDD (must be tied high)
or
Do Not Use (must be left floating)
5/5
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
5 Page 
Preliminary
GS88019/33/37AT-250/225/200/166/150/133
GS88019/33/37A Block Diagram
A0–An
Register
DQ
A0
A1
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
D0 Q0
D1 Q1
Counter
Load
A0
A1
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
A
Memory
Array
QD
36
4
36
E1
E2
E3
1
G
Power Down
ZZ
Control
Note: Only x36 version shown for simplicity.
Register
DQ
Register
DQ
1
DQx1–DQx9
Rev: 1.00 3/2002
6/24 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
11 Page | ||
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| PDF Descargar | [ Datasheet GS88019AT.PDF ] | |
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