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PDF AD9255 Data sheet ( Hoja de datos )

Número de pieza AD9255
Descripción 1.8 V Analog-to-Digital Converter
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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Data Sheet
14-Bit, 125 MSPS/105 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
AD9255
FEATURES
SNR = 78.3 dBFS at 70 MHz and 125 MSPS
SFDR = 93 dBc at 70 MHz and 125 MSPS
Low power: 371 mW at 125 MSPS
1.8 V analog supply operation
1.8 V CMOS or LVDS output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 300 MHz
−153.4 dBm/Hz small signal input noise with 200 Ω input
impedance at 70 MHz and 125 MSPS
Optional on-chip dither
Programmable internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Multimode digital receivers (3G)
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and
TD-SCDMA
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
PRODUCT HIGHLIGHTS
1. On-chip dither option for improved SFDR performance
with low power analog input.
2. Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
3. Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating 1.8 V CMOS or
LVDS outputs.
4. Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, test modes, and voltage
reference mode.
5. Pin compatibility with the AD9265, allowing a simple
migration up to 16 bits.
FUNCTIONAL BLOCK DIAGRAM
SENSE RBIAS PDWN AGND AVDD (1.8V)
LVDS LVDS_RS
VREF
VCM
VIN+
VIN–
DITHER
CLK+
CLK–
SYNC
REFERENCE
AD9255
TRACK-AND-HOLD
CLOCK
MANAGEMENT
ADC
14-BIT
14
CORE
OUTPUT
STAGING 14
CMOS OR
LVDS
(DDR)
SERIAL PORT
SVDD SCLK/ SDIO/ CSB
DFS DCS
Figure 1.
DRVDD (1.8V)
D13 TO D0
OR
OEB
DCO
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 page




AD9255 pdf
Data Sheet
AD9255
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS
enabled, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
SIGNAL-TO-NOISE-AND DISTORTION (SINAD)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
Without Dither (AIN at −23 dBFS)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
With On-Chip Dither (AIN at −23 dBFS)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
AD9255BCPZ-802 AD9255BCPZ-1052 AD9255BCPZ-1252
Temp Min Typ Max Min Typ Max Min Typ Max Unit
25°C 79.2
25°C 78.9
Full 78.1
25°C 78.0
25°C 76.9
78.9
78.5
77.6
77.7
76.4
78.3
78.3
76.9
77.1
75.5
dBFS
dBFS
dBFS
dBFS
dBFS
25°C 78.7
25°C 78.7
Full 77.9
25°C 76.8
25°C 75.8
78.6
78.0
77.3
77.0
75.3
78.0
78.0
76.7
76.7
74.3
dBFS
dBFS
dBFS
dBFS
dBFS
25°C 12.8 12.8 12.7 Bits
25°C 12.8 12.7 12.7 Bits
25°C 12.5 12.5 12.4 Bits
25°C 12.3 12.2 12.0 Bits
25°C −88 −90 −88 dBc
25°C −94 −89 −93 dBc
Full −91 −88 −85 dBc
25°C −82 −86 −89 dBc
25°C −81 −81 −80 dBc
25°C 88
25°C 94
Full 91
25°C 82
25°C 81
90
89
88
86
81
88
93
85
89
80
dBc
dBc
dBc
dBc
dBc
25°C 102
99
96 dBFS
25°C 103
97
99 dBFS
25°C 104
97
98 dBFS
25°C 102 101 97 dBFS
25°C 110 109 108 dBFS
25°C 110 108 109 dBFS
25°C 110 108 109 dBFS
25°C 110 109 109 dBFS
Rev. C | Page 5 of 44

5 Page





AD9255 arduino
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD9255
SYNC 1
CLK+ 2
CLK– 3
AVDD 4
AVDD 5
OEB 6
DNC 7
DCO 8
DNC 9
DNC 10
D0 (LSB) 11
D1 12
PIN 1
INDICATOR
AD9255
PARALLEL
CMOS
TOP VIEW
(Not to Scale)
36 AVDD
35 DITHER
34 AVDD
33 SVDD
32 CSB
31 SCLK/DFS
30 SDIO/DCS
29 DRVDD
28 DNC
27 OR
26 D13 (MSB)
25 D12
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE INPUT. THIS EXPOSED
PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 4. LFCSP Parallel CMOS Pin Configuration (Top View)
Table 8. Pin Function Descriptions (Parallel CMOS Mode)
Pin No.
Mnemonic
Type
Description
ADC Power Supplies
13, 20, 29
DRVDD
Supply
Digital Output Driver Supply (1.8 V Nominal).
4, 5, 34, 36, 45
AVDD
Supply
Analog Power Supply (1.8 V Nominal).
33
SVDD
Supply
SPI Input/Output Voltage
7, 9, 10, 28, 39, 40 DNC
Do Not Connect.
0
AGND
Ground
Analog Ground. The exposed thermal pad on the bottom of the package provides
the analog ground for the input. This exposed pad must be connected to ground for
proper operation.
ADC Analog
42
VIN+
Input
Differential Analog Input Pin (+).
43
VIN−
Input
Differential Analog Input Pin (−).
38
VREF
Input/output Voltage Reference Input/Output.
37
SENSE
Input
Voltage Reference Mode Select. See Table 11 for details.
47
RBIAS
Input/output External Reference Bias Resistor.
46
VCM
Output
Common-Mode Level Bias Output for Analog Inputs.
2
CLK+
Input
ADC Clock Input—True.
3
CLK−
Input
ADC Clock Input—Complement.
Digital Input
1
SYNC
Input
Digital Synchronization Pin. Slave mode only.
Digital Outputs
11
D0 (LSB)
Output
CMOS Output Data.
12
D1
Output
CMOS Output Data.
14
D2
Output
CMOS Output Data.
15
D3
Output
CMOS Output Data.
16
D4
Output
CMOS Output Data.
17
D5
Output
CMOS Output Data.
18
D6
Output
CMOS Output Data.
19
D7
Output
CMOS Output Data.
21
D8
Output
CMOS Output Data.
Rev. C | Page 11 of 44

11 Page







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