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PDF M180E2-L01 Data sheet ( Hoja de datos )
| Número de pieza | M180E2-L01 | |
| Descripción | LCD MODULE | |
| Fabricantes | CHI MEI | |
| Logotipo |  |
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Issued Date: Jul. 18, 2001
Model No.: M180E2 - L01
Approval
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item
Storage Temperature
Operating Ambient Temperature
Shock (Non-Operating)
Vibration (Non-Operating)
Altitude (Non-Operation)
Altitude (Operation)
Symbol
TST
TOP
SNOP
VNOP
Value
Min. Max.
-20 +60
0 +50
- 120
- 2.0
0 12,000
0 5,000
Note (1) Temperature and relative humidity range is shown in the figure below.
Unit Note
ºC (1)
ºC (1), (2)
G (3), (5)
G (4), (5)
M
M
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The temperature of panel display surface should be 0 ºC Min. and 60 ºC Max.
Note (3) 2ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 500 Hz, 0.5 Hr, 4 times each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough
so that the module would not be twisted or bent by the fixture.
Relative Humidity (%RH)
100
90
80
60
Operating Range
40
20
Storage Range
5
-40 -20
0 20 40
Temperature (ºC)
60 80
5 / 27
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Issued Date: Jul. 18, 2001
Model No.: M180E2 - L01
Approval
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE :
Pin Name
1 RXE3+
2 RXE3-
3 RXEC+
4 RXEC-
5 RXE2+
6 RXE2-
7 RXE1+
8 RXE1-
9 RXE0+
10 RXE0-
11 RXO3+
12 RXO3-
13 RXOC+
14 RXOC-
15 RXO2+
16 RXO2-
17 RXO1+
18 RXO1-
19 RXO0+
20 RXO0-
21 TEST
Description
Positive LVDS differential data input. Channel E3 (even)
Negative LVDS differential data input. Channel E3 (even)
Positive LVDS differential clock input. (even)
Negative LVDS differential clock input. (even)
Positive LVDS differential data input. Channel E2 (even)
Negative LVDS differential data input. Channel E2 (even)
Positive LVDS differential data input. Channel E1 (even)
Negative LVDS differential data input. Channel E1 (even)
Positive LVDS differential data input. Channel E0 (even)
Negative LVDS differential data input. Channel E0 (even)
Positive LVDS differential data input. Channel O3 (odd)
Negative LVDS differential data input. Channel O3(odd)
Positive LVDS differential clock input. (odd)
Negative LVDS differential clock input. (odd)
Positive LVDS differential data input. Channel O2 (odd)
Negative LVDS differential data input. Channel O2 (odd)
Positive LVDS differential data input. Channel O1 (odd)
Negative LVDS differential data input. Channel O1 (odd)
Positive LVDS differential data input. Channel O0 (odd)
Negative LVDS differential data input. Channel O0 (odd)
Test pin should be tied to ground.
Note (1) Connector(CN1) Part No.: JAE FI-TWE21PB-VF or equivalent.
Note (2) The first pixel is even.
Note (3) Input signal of even and odd clock should be the same timing.
Notes
First
Data
Second
Data
MODULE POWER CONNECTOR PIN :
Pin Name
1 GND
2 GND
3 GND
4 VCC
5 VCC
Description
Ground
Ground
Ground
+12.0 V power supply
+12.0 V power supply
Note (1) Connector(CN2) Part No.: JST-B5B-ZR-SM3-TF or equivalent.
Notes
11 / 27
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