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PDF 25LF020A Data sheet ( Hoja de datos )
| Número de pieza | 25LF020A | |
| Descripción | SST25LF020A | |
| Fabricantes | Silicon Storage Technology | |
| Logotipo |  |
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2 Mbit / 4 Mbit SPI Serial Flash
SST25LF020A / SST25LF040A
SST25LF020A / 040A2Mb / 4Mb Serial Peripheral Interface (SPI) flash memory
FEATURES:
Data Sheet
• Single 3.0-3.6V Read and Write Operations
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• 33 MHz Max Clock Frequency
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Read Current: 7 mA (typical)
– Standby Current: 8 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 70 ms (typical)
– Sector- or Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
– Software Status
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
– Write protection through Block-Protection bits in
status register
• Temperature Range
– Commercial: 0°C to +70°C
– Industrial: -40°C to +85°C
– Extended: -20°C to +85°C
• Packages Available
– 8-lead SOIC 150 mil body width
for SST25LF020A
– 8-lead SOIC 200 mil body width
for SST25LF040A
– 8-contact WSON (5mm x 6mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
SST’s serial flash family features a four-wire, SPI-com-
patible interface that allows for a low pin-count package
occupying less board space and ultimately lowering total
system costs. SST25LF020A/040A SPI serial flash
memories are manufactured with SST’s proprietary, high
performance CMOS SuperFlash technology. The split-
gate cell design and thick-oxide tunneling injector attain
better reliability and manufacturability compared with
alternate approaches.
The SST25LF020A/040A devices significantly improve
performance, while lowering power consumption. The
total energy consumed is a function of the applied volt-
age, current, and time of application. Since for any given
voltage range, the SuperFlash technology uses less cur-
rent to program and has a shorter erase time, the total
energy consumed during any Erase or Program operation
is less than alternative flash memory technologies. The
SST25LF020A/040A devices operate with a single 3.0-
3.6V power supply.
The SST25LF020A devices are offered in an 8-lead SOIC
150 mil body width (SA) package. The SST25LF040A
devices are offered in an 8-lead SOIC 200 mil body width
(S2A) package. All densities are offered in the 8-contact
WSON package. See Figure 1 for the pin assignments.
©2006 Silicon Storage Technology, Inc.
S71242-05-000
1/06
1
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
1 page  
2 Mbit / 4 Mbit SPI Serial Flash
SST25LF020A / SST25LF040A
Hold Operation
HOLD# pin is used to pause a serial sequence underway
with the SPI flash memory without resetting the clocking
sequence. To activate the HOLD# mode, CE# must be in
active low state. The HOLD# mode begins when the SCK
active low state coincides with the falling edge of the
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD# signal does not
Data Sheet
coincide with the SCK active low state, then the device
exits in Hold mode when the SCK next reaches the active
low state. See Figure 3 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, it resets
the internal logic of the device. As long as HOLD# signal is
low, the memory remains in the Hold condition. To resume
communication with the device, HOLD# must be driven
active high, and CE# must be driven active low. See Figure
18 for Hold timing.
SCK
HOLD#
Active
Hold
FIGURE 3: HOLD CONDITION WAVEFORM
Active
Hold
Active
1242 F03.0
Write Protection
SST25LF020A/040A provides software Write protection.
The Write Protect pin (WP#) enables or disables the lock-
down function of the status register. The Block-Protection
bits (BP1, BP0, and BPL) in the status register provide
Write protection to the memory array and the status regis-
ter. See Table 5 for Block-Protection description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down func-
tion of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 3). When WP# is high, the lock-down func-
tion of the BPL bit is disabled.
TABLE 3: CONDITIONS TO EXECUTE WRITE-STATUS-
REGISTER (WRSR) INSTRUCTION
WP#
L
L
H
BPL
1
0
X
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
T3.0 1242
©2006 Silicon Storage Technology, Inc.
5
S71242-05-000
1/06
5 Page 
2 Mbit / 4 Mbit SPI Serial Flash
SST25LF020A / SST25LF040A
Byte-Program
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte must
be in the erased state (FFH) when initiating a Program
operation. A Byte-Program instruction applied to a pro-
tected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active low
for the duration of the Byte-Program instruction. The Byte-
Data Sheet
Program instruction is initiated by executing an 8-bit com-
mand, 02H, followed by address bits [A23-A0]. Following the
address, the data is input in order from MSB (bit 7) to LSB
(bit 0). CE# must be driven high before the instruction is
executed. The user may poll the Busy bit in the software
status register or wait TBP for the completion of the internal
self-timed Byte-Program operation. See Figure 6 for the
Byte-Program sequence.
CE#
MODE 3
SCK MODE 0
0 1 2345 6 78
15 16
23 24 31 32 39
SI 02
MSB
SO
FIGURE 6: BYTE-PROGRAM SEQUENCE
ADD.
MSB
ADD.
HIGH IMPEDANCE
ADD. DIN
MSB LSB
1242 F06.0
©2006 Silicon Storage Technology, Inc.
11
S71242-05-000
1/06
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet 25LF020A.PDF ] | |
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