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PDF L6611 Data sheet ( Hoja de datos )

Número de pieza L6611
Descripción DIGITALLY PROGRAMMABLE SECONDARY HOUSEKEEPING CONTROLLER
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! L6611 Hoja de datos, Descripción, Manual

L6611
DIGITALLY PROGRAMMABLE SECONDARY
HOUSEKEEPING CONTROLLER
s OV/UV DETECTION FOR 3.3V, +5V, ±12V
RAILS AND 5V (OR 3.3V) AUX. VOLTAGE
s AC MAINS UV (BROWNOUT) DETECTION
WITH HYSTERESIS
s ON-LINE DIGITAL TRIMMING FOR 5V/12V,
3.3V, 5V (OR 3.3V) AUX. FEEDBACK
REFERENCES AND AC MAINS UV.
s DIGITALLY SELECTABLE OPTIONS
s ERROR AMPLIFIERS FOR 5V/12V RAILS
(MAIN SUPPLY), 3V3 POST-REGULATOR
(MAG_AMP OR LINEAR) AND AUXILIARY
SUPPLY.
s MAIN SUPPLY ON/OFF CONTROL AND
POWER GOOD SIGNAL
s 50mA CROWBAR DRIVE FOR AUXILIARY
OUTPUT OVP.
s OPEN GROUND PROTECTION
s 8ms DIGITAL SOFT START
s 64 ms UV/OC BLANKING AT START-UP
TYPICAL APPLICATION CIRCUIT
WIDE RANGE
MAINS
+
-
MAIN
CONTROL
BCD TECHNOLOGY
DIP20
SO20
ORDERING NUMBERS:
L6611N
L6611D
L6611DTR(T & Reel)
APPLICATIONS
s SWITCHING POWER SUPPLIES FOR
DESKTOP PC'S, SERVERS AND WEB
SERVERS
s SUPERVISOR FOR DISTRIBUTED POWER
+12V
+5V
COM
-12V
+3.3V
+5Vaux
April 2002
AUXILIARY
CONTROL
Bout
VDD
Dmon
Cout
12V
5V
MFault
-12V
3V3
Aout
Gnd
L6611
1/28

1 page




L6611 pdf
L6611
PIN DESCRIPTION (continued)
Pin # Name
Description
18 3V3 3V3 UV/OV monitor. It uses a separate reference to the feedback reference.
Input pin for 5V feedback, 5V current sense and 5V UV/OV monitor. 5V UV/OV uses a reference
19 5V separate from that used for feedback. This pin connects the 5V part of the Main error amplifier
feedback divider.
Input pin for 12V feedback, 12V current sense and 12V UV/OV monitor.12V UV/OV uses a
20 12V reference separate from that used for feedback. This pin connects the 12V part of the Main error
amplifier feedback divider.
FUNCTION DESCRIPTION
Name
Description
OVP
Whenever one of the Main output voltages is detected going above its own OVP threshold, this
function set MFAULT (#1) high latching the outputs off. The latch is released after cycling PS-ON
(#13) switch or by reducing Vdd (#10) below the UV threshold.
UVP
Whenever one of the Main output voltages is detected going under its own UVP threshold, this
function sets MFAULT (#1) high; if latch mode has been selected, this function will be latched.
Otherwise an attempt will be made to restart the device after 1 second delay. If ACsns (#11) is
low due to a brownout condition, UVP is disabled.
UVB
Undervoltage blanking. When either converter is enabled, the relevant UV/OC monitoring circuits
must not intervene to allow all outputs to come within tolerance. 64 ms timing is provided; for the
auxiliary converter the timing starts as the IC has a valid supply, for the main converter it starts
as the ACsns pin detects a valid input voltage for the converter.
PW-OK delay
PW-OK delay. After power-up, when the all of the monitored voltages are above their own UV
threshold the PW-OK pin (#12) will be kept low for additional 250ms (typ.) to make sure all the
outputs are settled.
OFF delay
Power-off delay. As soon as PS-ON (#13) pin is recognized high, indicating an imminent turn-off
condition, PW-OK (#12) pin will go low immediately . The converter will be turned off after a
delay of 2.5ms.
Debounce
The PS-ON signal input has debounce logic to prevent improper activation. All of the monitored
inputs have digital filtering/debounce logic on board for high noise immunity.
AC-hysteresis
AC sense hysteresis. Programmable hysteresis is provided on the ACsns input (#11) to avoid
undesired shutdown caused by noise as the voltage at the pin is near the threshold or by the
voltage ripple across the bulk capacitor.
Vdd-OVP
Vdd is monitored for overvoltage. If an overvoltage is detected, MFAULT (#1) and DFAULT (#9)
are latched high.
Vdd-UVL
To prevent false signals of any of IC’s output pins, an under voltage lock-out circuit monitors Vdd
and keeps all IC’s output at their default OFF level until Vdd reaches a sufficient minimum
voltage for ensuring integrity. When Vdd goes below the UV threshold, all latches are reset and
volatile programming memory cleared.
Dual-OVP
Dmon (#8) is monitored to detect an overvoltage condition; in this case MFAULT (#1) and
DFAULT (#9) are latched high.
Dual-UVP
Dmon (#8) is monitored to detect an undervoltage condition; in this case MFAULT (#1) is latched
high and Cout (#6) is pulled low.
5/28

5 Page





L6611 arduino
L6611
ELECTRICAL CHARACTERISTCS (continued)
(unless otherwise specified: TJ = 0 to 105°C; VDD = 5V, V3V3 = 3.3V, V5V = 5V, V-12V = -12V, ,
VDmon = VDD, PS-ON = low)
Symbol
Parameter
Test Condition
Min. Typ.
FCLOCK Clock Frequency
VDATALO Data Input Low
VDATAHI Data Input High
2
IFUSE PROM Fuse Current
400
tFUSE PROM Fusing Time
3
Max.
0.8
1.5
Unit
MHz
V
V
mA
ms
11/28

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