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PDF L6256 Data sheet ( Hoja de datos )

Número de pieza L6256
Descripción 12V COMBO
Fabricantes STMicroelectronics 
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L6256
12V COMBO
DESCRIPTION
The 12 Volt Combo chip is a combination spindle
motor driver, voice coil driver and D/A converter.
The part can be used in,application like HDD.
The VCM amplifiers drive a low impedance coil
and are set up to accept RC compensation, which
allows a wide bandwidth with absolute minimum
phase lag. The sense resistor/amplifier arrange-
ment allows full current loop operation. The loop
gain is changeable by attenuating the VCM DAC
voltage amplitude in cascadable stages.
The Spindle driver is a PWM only voltage loop
with power supply feedforward, driving a 3 phase
sensorless brushless DC motor. Since it uses
PWM operation at full run speed, it has output
slew rate control during start and run modes.
There is an inductive clamp circuit to limit flyback
voltage transients across the supply voltage dur-
ing motor phase changes and during the braking
sequence. Only the 2 phase or bipolar commuta-
tion pattern is produced by the internal commuta-
tion circuitry. A commutation register allows arbi-
Figure 1. Block Diagram
PLCC44
ORDERING NUMBER: L6256
trary winding sequencing during certain opera-
tions. Internal protection against crossover
spikes is built in.
3 phase or tripolar commutation can be supported
in software during start by writing a commutation
pattern directly to the preload register.
Tripolar operation requires that more than two
phase drivers contribute current simultaneously.
The current limit circuitry reflects this and allows
33% higher current limit, which produces nearly
CP_OUT
CP_CAP
18
19
33
H_VPWR
VDD
VCC
nPOR
POR_RC
PARK
34
15
10
9
27
13
SCLK
SDIO
CSELB
14
28
BYPASSC 16
CHARGE
PUMP
DAC
32
IO_VC
31
I_VC
26
A_IN
30
A_OUT B_OUT
25 23
VCM CLASS AB
DRIVERS
VPWR
2
UV
DETECT
POR
10 BIT
DAC
VCM
COMMAND
CHANNEL
VCM CONTROL
VCM
RETRACT
h_vpwr
VCM
LOGIC
THERMAL
-
+
A
AMP
PWR GND
-
+
h_vpwr
B
AMP
CLK
SYNC
SERIAL INTERFACE
3
BANDGAP
VOLTAGE
REFERENCE
CURRENT
SOURCES
SPINDLE LOGIC
SPINDLE SEQUENCER
BRAKE
DELAY
COUNTER
DYNAMIC
CLAMPING
SPINDLE DRIVERS
ANALOG
TEST MUX
24
SYNC
CLAMP
3
QDRIVE
VREG_IN
CUR_IN
20
21
22
3.3V LINEAR
REGULATOR
6,7,17,29,39,40
FEEDFORWARD
COMPENSATION
upper
lower
PRE-DRIVERS
8 11
R_ PWM_
SLEW IN
36 37 5
PWM_ FF_ SP_
DC COMP CLK
BEMF SENSING
ZERO CROSSING
DETECTION
CURRENT
LIMIT
SENSING
38 12
35
SH_ BEMF_ REF_
OUT DET
IN
44
SP_
G2
4
SP_
G1
24
VC_PWR
2
SP_P1
42
SP_P2
43
SP_A
1
SP_B
3
SP_C
41
C_TAP
D97IN571
December 1997
1/28

1 page




L6256 pdf
GENERAL BLOCK DESCRIPTIONS
(see figure 1)
Charge Pump
The Charge Pump provides bias for the upper driv-
ers, for the brake circuit, and for internal circuitry as
required for normal and spindown operation. Slew
rate control is built in for quiet operation.
Serial Interface
The serial interface will transfer all control, status
and data to and from the processor. Internal test-
ing provisions have also been made through this
port. The interface is compatible with an
8X196MP,NU or K17 series processor at low
speed only, due to internal limitations of the proc-
essors. External chip select is mandatory on the
L6256. Chip Select is also used to reset and syn-
chronize the serial port. The serial port is used to
indicate thermal shutdown of the Dolphin chip.
Brake Delay Timer
The brake delay will, upon start of a park or brake
sequence, delay 128 negative zero crossings of
the A spindle phase to allow the park circuit to op-
erate. (The delay will typically be on the order of
400 msecs.) Then the braking sequence can be-
gin. The output of this timer is provided to the se-
rial port registers to indicate the start of the brake
action, and to indicate the start and end of the
park period.
3.3V Regulator
The 3.3V external regulator provides a logic 3.3V
using an external pass element (N channel FET),
tied into the undervoltage detection system. It has
the following features:
Voltage mode control, using no external com-
pensation.
3:1 foldback current limit to protect the pass
element in case of component failure.
Absolute regulation of 8% under all operating
conditions
Control Registers
See serial port section.
Internal Testing
This circuitry is per vendor’s specifications. No
test functions actuated by the serial port software
allow chip or drive damage to inadvertently occur.
Double level write enabling is used. Differing ven-
dor test requirements are accomodated using the
unique vendor code bits. Various external pins
are used for this function; consult the manufac-
turer’s data sheets.
L6256
Spindle Section
SPINDLE CURRENT LIMIT
The spindle current limit value in start mode is set
by the value of the external resistor on the Ref_In
pin during start (which at start is shorted to Vcc,
and the current out of the pin sets the current limit
value).
During run, various internal methods are used to
set a nominal maximum current value for circuit
protection only. Consult the data sheets and ap-
plication notes for a description of this circuitry.
Current limit operates on a cycle by cycle basis.
The current limit comparator output is provided to
the serial port to indicate when the spindle is in
current limit. The current limit bit is reset when
the status register is read.
NOTE: Current limit operation involves chaotic
states, and careful firmware control can be used,
if desired, to prevent audible squels. Actual cur-
rent limit value is also affected significantly by
motor inductance. See application notes.
COMMUTATION COUNTER (CCTR)
The Commutation Counter provides commutation
control for the spindle motor. It advances the
spindle phases according to the bipolar phase
control sequence, every time a SPIN_CLK posi-
tive edge is received. Its reset state (B C\) is gov-
erned by the Commutation Preload Register
(CPR). Operation of the register is synchronous
with SP_CLK, but the reset is asynchronous.
COMMUTATION PRELOAD REGISTER (CPR)
During the initial start period, phase on/off control
is preloaded into the counters from the Commuta-
tion Preload Register, which is loaded from the
serial port. This allows direct commutation con-
trol from the processor. Various commutation
schemes are implemented during startup by soft-
ware through this register. High side bits take
precedence over low side bits.
For both high and low drivers, logic high input to
this register turns on the respective driver. Any
pattern other than all 1’s holds the CCTR in reset,
and sets the MUX to bring data from the CPR
register for the drive pattern. An all 1’s pattern
(an illegal state) releases the CCTR reset and
switches the MUX to read the CCTR.
An all 0 pattern in the CPR spindle control bits
both tristates the spindle drivers and resets the
commutation counter.
The commutation latch holds data from either the
CPR or the CCTR depending on whether all 1’s
are loaded into the CPR. The latch loads the pre-
vious state of the counter when the SP_CLK edge
comes in. The latch circuitry also provides chop
commutation information.
5/28

5 Page





L6256 arduino
Read and write clock rates may differ by as much
as 2:1. Clock rates may differ between different
chips using the bus.
A logic inversion may be used by other chips on
the bus. If this is done, use of the chip select line
after transmissions to the other chips is manda-
tory.
Chip Select
The external chip select masks out any incoming
data. When inactive, the serial port bit clocking
state machine is cleared, providing a resync
mechanism. The chip select may not change
states between every packet transmission, so it
should not be counted on as a continuous signal.
If the Dolphin is the only chip on the serial port,
the chip select will only be used an emergency re-
sync if the chip doesn’t answer queries.
Figure 5. Serial Port Chip Select Operation.
L6256
If an address byte is received that is not ad-
dressed to the Dolphin while chip select is active,
the Dolphin will ignore the transmission.
A metal option in the chip select circuit will allow
for either polarity of active level. Present intention
is for an active high level on the chip select pin.
Logic Inversion on Serial Port
If a logic inversion is used by other chips on the
serial bus, the R/W bit will assume the wrong
state and the Dolphin state mechanism will lose
synchronization. In this situation, it will be manda-
tory for the processor to deassert the chip select
to mask the serial port data intended for the other
chip.
Typical bus waveforms are shown below, with the
resultant activity.
1) Block Mode Write - To other chip
A1
SCLK
D
SDIO
wrong
address
CSELB
(A1 and A2 ignored)
2) Valid Writes to L6256
A1
SCLK
D
SDIO
CSELB
B
(All Data Written)
A2 D
A2 D
D97IN588
11/28

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