PDF L6238SQT Data sheet ( Hoja de datos )

Número de pieza	L6238SQT
Descripción	12V SENSORLESS SPINDLE MOTOR CONTROLLER
Fabricantes	STMicroelectronics
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No Preview Available ! L6238S 12V SENSORLESS SPINDLE MOTOR CONTROLLER PRODUCT PREVIEW 12V OPERATION 3A, THREE-PHASE DMOS OUTPUT (TOTAL Rdson 0.52Ω) NO HALL SENSORS REQUIRED DIGITAL BEMF PROCESSING LINEAR OR PWM CONTROL STAND ALONE OR EXT. DRIVER SHOOT-THROUGH PROTECTION THERMAL SHUTDOWN PLCC44 PQFP44 DESCRIPTION The L6238S is a Three-Phase, D.C. Brushless Spindle Motor Driver system. This device features both the Power and Sequence Sections. Higher Power Applications can be activied with the addition of an external Linear Driver, or by op- erating the Internal Drivers in PWM. Motor Start-Up, without the use of Hall Sensors, can be achieved either by an internal start-up al- gorithm or by manually sequencing the Output Drivers, using a variety of User-Defined Start-UP Algorithms. BLOCK DIAGRAM TQF P64 ORDERING NUMBERS: L6238S (PLCC44) L6238SQA (PQFP44) L6238SQT (TQFP64) Protection features include Stuck Rotor\Backward Rotation Detection and Automatic Thermal Shut- down. VANALOG SYS CLOCK SEQ INCR MONO/SEQ CTRL TDLY(0) TDLY(1) TDLY(2) MASK DLY SPIN SENSE OT-WARN VL BIAS SYSTEM CLOCK FALIGN OUTPUT ENABLE RUN/ PWM/ PWM PWM PWM BRAKE SLEW LIN COMP TIM ALIGN + GO START-UP ONE-SHOT SLEW-CTRL CHARGE PUMP POWER STAGE DIGITAL DELAY MONO DET SEQUENCER ZERO CROSSING DETECTOR + BEMF + SENSE + - TOGGLE THERMAL SHUTDOWM DIVIDE BY N + - DRV CNTL AV=4V/V CSA SEL POL FMTR VCTRL GM COMP GATE DRIVE D95IN232 CPUMP1 CPUMP2 CPUMP3 VPOWER BRAKE DELAY OUT A OUT B OUT C CTR TAP RSENSE1 RSENSE2 GND CSA INPUT October 1995 1/31 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1 page L6238S PIN FUNCTIONS PLCC44 PQFP44 TQFP64 Name I/O Function 38 32 45 GATE DRIVER I/O Drivers the Ext. PFET Gate Driver for Higher Power applications. This pin must be grounded if an external driver is not used. 41 35 51 MASK/DELAY O Internal Logic Signals used for production Testing 43 37 54 CENTER TAP I Motor Center Tap used for differential BEMF sensing. 44 38 55 PWM/SLEW I R/C at this input set the Linear Slew Rate and PWM OFF-Time Figure 1: Brake Delay Timeout vs Cbrake (Rbrake = 1Meg) TBD (s) D95IN274 3.0 1.0 Figure 2: Linear Slew Rate vs Rslew SVR (V/µs) D95IN275 3.0 1.0 0.3 0.3 0.0 0.0 0.3 1.0 3.0 Cb(µF) Figure 3: PWM Off - Time vs Rslew/Coff 0.0 10 30 100 300 Rs(KΩ) Figure 4: PWM Limit Time - Out vs Ctimer PWM (µs) 30 D95IN276 PWM (µs) D95IN277 10 3 1 100 30 10 300 Coff(pF) 100 300 Ctimer(pF) 5/31 5 Page Figure 2.2 POR=0 FROM ANY STATE RUN/BRK=0 FROM ANY STATE STATE=1 DRIVERS OFF MIN CLOCK DELAY PERIOD STOP DELAY STOP MASK STOP RUN/BRAKE=1 DRIVERS OFF MIN CLOCK DELAY LOAD MIN DELAY LOAD MIN MASK PERIOD STOP DELAY COUNT STATE=STATE+1 MASK COUNT OUTENA=1 CHECK FOR Zc 2 21 SYS_CLK DRIVERS ON PERIOD STOP DELAY STOP MASK STOP 64/FALIGN CHECK FOR Zc 192/FALIGN STATE=STATE+1 LOAD DELAY=MIN LOAD MASK=MAX PERIOD COUNT DELAY COUNT STATE=STATE+1 MASK COUNT BEMF DRIVERS ON LOAD DELAY=PERIOD LOAD MASK=PERIOD RESET PERIOD PERIOD COUNT DELAY COUNT* STATE=STATE+1 MASK COUNT BEMF: BEMF RISING WITH PNSLOPE=1 OR BEMF FALLING WITH PNSLOPE=0 BEMF: BEMF RISING WITH PNSLOPE=0 OR BEMF FALLING WITH PNSLOPE=1 *MIN MASK=192/SYS_CLK (I.E. WITH SYS_CLK=10MHz, MIN MASK=19.2µs) BEMF BEMF D95IN310 L6238S Bemf. This resychronization can either occur whenever Output Enable or Run/Brake is first brought low then high. Referring to figure 2-4, the ”Hold for Resync” state is brought low. The controller leaves this state and enters ”Start Resync” when Output En- able is high. Figure 2.3: Watch-Dog Timer OVER TEMP SHUTDOWN OUTPUT RUN/ ENABLE BRAKE FALIGN S TO START-UP Q LOGIC Q S D95IN311 Figure 2-4 BEMF BEMF RUN/BRK=0 LOAD MIN DELAY LOAD MIN MASK* DELAY COUNT STATE=STATE+1 MASK COUNT OUTENA=1 CHECK FOR Zc BEMF LOAD DELAY=MIN LOAD MASK=MIN PERIOD COUNT DELAY COUNT* STATE=STATE+1 MASK COUNT DRIVERS OFF MONO=0** BEMF OUTENA=1 BEMF BEMF RUN MODE DRIVERS ON LOAD DELAY=PERIOD LOAD MASK=PERIOD RESET PERIOD PERIOD COUNT DELAYH COUNT* STATE=STATE+1 MASK COUNT OUTENA=0 RESYNCHRONIZATION MODE DRIVERS OFF MIN CLOCK DELAY PERIOD STOP HOLD FOR RESYNC D95IN312 CLOCK DELAY=(TDLY [2:0] WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED>12.7Hz FOR 8 POLES) BEMF: BEMF RISING WITH PNSLOPE=1 OR BEMF FALLING WITH PNSLOPE=0 BEMF: BEMF RISING WITH PNSLOPE=0 OR BEMF FALLING WITH PNSLOPE=1 * MONO=0 WHEN FREQ (BEMF)=2FREQ(PHASE) ** MIN MASK=192/SYS_CLK(I.E.WITH SYS_CLK=10MHz, MIN MASK=19.2µs) 11/31 11 Page

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