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PDF GP4020 Data sheet ( Hoja de datos )

Número de pieza GP4020
Descripción GPS Receiver Baseband Processor
Fabricantes Zarlink Semiconductor Inc 
Logotipo Zarlink Semiconductor Inc Logotipo



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No Preview Available ! GP4020 Hoja de datos, Descripción, Manual

GP4020
GPS Receiver Baseband Processor
Features
• Complete GPS correlator and Firefly MF1
microcontroller core
• ARM 7TDMITM (Thumb®) Microprocessor, with JTAG
ICEBreakerTM Debug Interface
• Fully Configurable External Data Bus
• 12 Fully Independent Correlation Channels
• Low Voltage Operation: 3·3V
• Low Current Power–Down Mode
• 1PPS UTC Aligned Timing Output
• Dual UART
• 3-wire BµILD Serial Input/Output (BSIO) Interface
• 8 General Purpose Input/Output (GPIO) Lines
• Boot ROM, allowing Software Upload via UART
• 8K Bytes Internal SRAM
• Compatible with GP2015 and GP2010 RF Front Ends
Applications
GPS Navigation Systems
GPS Geodetic Receivers
Time Transfer Receivers
Automatic Vehicle Location (AVL)
E911 Emergency Positioning
Related Products
Part Description
GP2015
GP2010
GPS Receiver RF Front End
(TQFP 48 package)
GPS Receiver RF Front End
(PQFP 44 package)
Data sheet
DS4374
DS4056
DS5134
ISSUE 4.4
May 2002
Ordering Information
GP4020/IG/GQ1N (trays)
GP4020/IG/GQ1Q (tape and reel, 1000 units per reel)
The GP4020 is available in a 100 pin PQFP package in
Industrial (-40°C to +85°C) grade. The ordering code is
standard for screened devices
Description
The GP4020 is a complete digital baseband processor
for a Global Positioning System (GPS) receiver. It
combines the 12-channel correlator function of the
GP2021 with an advanced ARM7TDMI (Thumb)
microprocessor to achieve a higher level of integration,
reduced system cost, reduced power consumption and
added functionality. The GP4020 complements the
GP2015 and GP2010 C/A code RF downconverters
available from Zarlink Semiconductor.
The correlator section contains 12 identical tracking
module blocks, one for each channel. Each channel
contains all the components necessary for acquiring
and tracking the received signal, and also contains
other functional blocks, which are used to produce part
of the measurement data set. Individual channels may
be deactivated for systems not requiring full 12-channel
operation and thus allowing for reduced power
consumption and processor loading.
The microprocessor section contains the Firefly MF1
microcontroller core, which includes an ARM7TDMI
with a Thumb instruction de-compressor plus the Firefly
BµILD module. Also included are a second UART,
BµILD Serial I/O, General I/O and Watchdog functions.
Absolute Maximum Ratings
Supply voltage (VDD) from ground (GND)
Bias for 5V inputs
Input voltage (any input pin)
Output voltage (any output pin)
Storage temperature
Static discharge (HBM)*
-0·5V to +5·0V
+7·0V max.
GND-0·5V to VDD+0·5V
GND-0·5V to VDD+0·5V
-55°C to +150°C
2kV
*Mil Std 883 Human Body Model = discharge from 100pF through
1500between any 2 pins
Manufactured under licence from ARM Ltd
ARM and the ARM logo are trademarks of Advanced RISC Machines Ltd

1 page




GP4020 pdf
GP4020
Pin No. Signal name
Type
Associated
circuit block
Description
Notes
60
GND
PWR
61 SIGN0
I
62 MAG0
I
63 SAMPCLK
O
64 POWER_GOOD
I
65 PR_XOUT
O
66 PR_XIN
I
67 TEST
I
68 VDD PWR
69 TIMEMARK / TIC
O
70 IDDQTEST
I
71
GND
PWR
72 RTC_XIN
I
73 RTC_XOUT
O
74 TESTMODE
I
75 NSRESET
I
76 U2TXD
O
77 U2RXD
I
78 U1TXD
O
79 U1RXD
I
80
PLLGND
PWR
81
PLLVDD
PWR
82
GND
PWR
83 PLLAT1
O
84 NICE
I
85 VDD PWR
86 TCK/bdiag[0]/XReq I/O
87 TDI/bdiag[1]/XWrite I/O
88 TDO/bdiag[2]/XBurst I/O
CORR
CORR
CORR
PCL
SCG
SCG
1PPS
RTC
RTC
PCL
UART2
UART2
UART1
UART1
SCGPLL
SCGPLL
SCGPLL
JTAG/SSM
MUTIPLEX
JTAG/SSM
JTAG/SSM
JTAG/SSM
Sampled Sign (polarity) data from RF front end.
Sampled Mag (amplitude) data from RF front
end.
SampleClockoutputtotheRFfrontend.Provides
a 5·714MHz clock with a 4:3 mark to space ratio.
Power Monitor input, high for normal operation;
low forces the GP4020 into Power Down mode.
System Clock Oscillator - crystal output for 10 to
16MHz crystal.
System Clock Oscillator - crystal inputfor 10 to
16MHz crystal.
TEST select pin,used with TESTMODE (pin 74).
Used for test purposes only and should be
connected to GND in normal operation.
Timemarkoutput.Thispincanbeusedtoproduce
a UTC-aligned 1 PPS output, or TIC output.
TEST select pin,used with TESTMODE (pin 74).
Used for test purposes only and should be
connected to GND in normal operation.
Real-timeClockOscillatorinputfor32kHzcrystal.
Real-timeClockOscillatoroutputfor32kHzcrystal.
TEST select pin,used with TEST (pin 67). Used
for test purposes only and should be connected
to GND in normal operation.
System Reset input.
UART 2 Transmit data output.
UART 2 Receive data input.
UART 1 Transmit data output.
UART 1 Receive data input.
GND connection for PLL Block.
VDD connection for PLL Block.
System Clock Generator PLL Analog Test I/O.
Reserved for TEST purposes only and should
NOT be connected in normal operation.
ARM7 operating mode and JTAG / SSM Signal
Multiplex (pins 86, 87, 88, 89).
JTAG Test Clock/SSM Diagnostic broadcast
debug output bdiag[0]/System test control input
XReq.
JTAG Test Data In/SSM Diagnostic broadcast
debug output bdiag[1]/System Test control input
X/Write.
JTAG Test Data Out/SSM Diagnostic broadcast
debug output bdiag[2]/System test control input
XBurst.
5
5
3
3
6
6
6
6
Table 1 - Pin descriptions (continued)
Cont…
5

5 Page





GP4020 arduino
GP4020
Since the memory is high-speed, it can be accessed
with Zero wait-states through the Memory Peripheral
Controller. Refer to section on the Memory Peripheral
Controller for more information.
Real Time Clock (RTC)
The GP4020 Real Time Clock uses an external 32kHz
crystal to give an indication of time to the GP4020 chip,
when the device is in Reset / Power Down. If a backup
battery is included in a GPS receiver using the GP4020,
the RTC will continue to operate regardless of the reset
state of the rest of the device.
The RTC is incremental, which means that the number
of seconds from a reset point are accumulated, rather
than a record of Gregorian date.
System Clock Generator (SCG)
The GP4020 System Clock Generator is used to
provide 2 system clocks:
• The M_CLK for the 12-channel Correlator; this is
derived from the CLK_T and CLK_I inputs from the
RF front end device and MUST be 40MHz. This
clock is fundamental to the correlator function, and
must be phase-locked to the RF front end.
The BµILD_CLK for ALL components on the BµILD
Bus; this can be derived from M_CLK (see above) in
conjunction with a PLL and a divider to generate a
wide range of clock frequencies. In this way, the
BµILD_CLK can be phase-locked to the RF front end.
The clock can also be derived from an independent
crystal source.
System Services Module (SSM)
The System Services Module (SSM) ensures correct
bus operation through a number of modes (reset,
initialisation, debug, etc). It provides diagnostic
broadcast of address and data for internal transfers
along with information about the current operating
mode.
Additionally the SSM System Configuration Register
controls the operating mode of the GP4020.
Specifically the System Services Module performs the
following functions:
• Control the BµILD bus operational mode
• Arbitrate amongst competing resources for BµILD
bus mastership
• Interface to external bus masters and
manufacturing testers
• Control the activities of all BµILD bus modules during
system debug activity.
• Broadcast information about BµILD bus activity for
external diagnostics
• Hold BµILD bus logic levels when no other bus-
master is driving
• Register System Configuration data
System Timer/Counters (SYSTIC)
Two dual independent 32-bit timer/counters, with an 8-
bit pre-scaler capability for each counter, are provided
(Timers 1A, 1B, 2A and 2B). These are synchronous to
the system clock and may be polled, or set-up to
generate interrupts on over-run, with auto-reload.
The TIC functions provided by this module are part of
the Firefly MF1 core. Timer 1 (TIC1) appears at GP4020
Base Address 0xE000 E000, and Timer 2 (TIC2)
appears at Address 0xE000 F000. TIC enable (TEN)
lines are not available externally on this version of the
GP4020, but are tied low on-chip. The TIC functions can
be made available by setting the External enable
polarity bit of the TIC Control/Status register to a logic
‘0’.
Whilst these timer/counters are NOT required by the
GPS function in a GP4020 based GPS receiver, full
programming details of the programming of the System
Timer/Counter can be found in Section 7 of the Firefly
MF1 Core Design Manual.
1PPS Timemark Generator
The GP4020 Timemark generator is used in conjunction
with software to produce a 1 Pulse Per Second (1PPS)
output pulse, which is aligned to Universal
Time Co-ordinated (UTC) to a resolution of 25ns. The
accuracy of time transmitted from the Navstar GPS
space segment is very high, and this can be used to
provide a mobile timing reference to a similar accuracy.
Up Integration Module (UIM)
The Up Integration Module provides a series of internal
connection ports, which mimic the MPC external
interface. This allows the Firefly MF1 to communicate
with the Application Specific Logic used in the GP4020,
as though it was external to the chip, hence it acts as a
transparent interface.
11

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