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PDF GMS30C2132 Data sheet ( Hoja de datos )
| Número de pieza | GMS30C2132 | |
| Descripción | USERS MANUAL | |
| Fabricantes | Hynix Semiconductor | |
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Hay una vista previa y un enlace de descarga de GMS30C2132 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Jun 13, 2001
Ver. 3.1
16/32 BIT RISC/DSP
GMS30C2116
GMS30C2132
USER’S MANUAL
1 page  
TABLE OF CONTENTS
i
Table of Contents
0. Overview
0.1 GMS30C2116/32 RISC/DSP.............................................................................. 0-1
0.2 Block Diagram.................................................................................................... 0-6
0.3 Pin Configuration................................................................................................ 0-7
0.3.1 GMS30C2132, 160-Pin MQFP-Package - View from Top Side ........ 0-7
0.3.2 Pin Cross Reference by Pin Name ...................................................... 0-8
0.3.3 Pin Fuction .......................................................................................... 0-9
1. Architecture
1.1 Introduction...................................................................................................... 1-1
1.1.1 RISC Architecture ............................................................................... 1-1
1.1.2 Techniques to reduce CPI (Cycles per Instruction)............................. 1-2
1.1.3 The pipeline structure of GMS30C2132 ............................................. 1-6
1.2 Global Register Set .......................................................................................... 1-7
1.2.1 Program Counter PC, G0 .................................................................... 1-8
1.2.2 Status Register SR, G1 ........................................................................ 1-9
1.2.3 Floating-Point Exception Register FER, G2 ..................................... 1-12
1.2.4 Stack Pointer SP, G18 ....................................................................... 1-13
1.2.5 Upper Stack Bound UB, G19 ............................................................ 1-13
1.2.6 Bus Control Register BCR, G20 ....................................................... 1-13
1.2.7 Timer Prescaler Register TPR, G21 .................................................. 1-14
1.2.8 Timer Compare Register TCR, G22.................................................. 1-14
1.2.9 Timer Register TR, G23.................................................................... 1-14
1.2.10 Watchdog Compare Register WCR, G24........................................ 1-14
1.2.11 Input Status Register ISR, G25 ....................................................... 1-14
1.2.12 Function Control Register FCR, G26.............................................. 1-14
1.2.13 Memory Control Register MCR, G27............................................. 1-15
1.3 Local Register Set.......................................................................................... 1-15
1.4 Privilege States .............................................................................................. 1-16
1.5 Register Data Types....................................................................................... 1-17
1.6 Memory Organization.................................................................................... 1-18
1.7 Stack............................................................................................................... 1-20
1.8 Instruction Cache ........................................................................................... 1-25
1.9 On-Chip Memory (IRAM)............................................................................. 1-28
5 Page 
Overview
0. Overview
0-1
0.1 GMS30C2116/32 RISC/DSP
The GMS30C2116 and GMS30C2132 RISC/DSP present a new class of microprocessors:
The combination of a high-performance RISC microprocessor with an additional powerful
DSP instruction set and on-chip micro-controller functions. The high throughput is not
achieved by raw clock speed, it is due to a sophisticated novel architecture, combining the
advantages of RISC and DSP technology.
The speed is obtained by an optimized combination of the following features:
¡ Ü The most recent stack frames are kept in a register stack, thereby reducing data memory
accesses to a minimum by keeping almost all local data in registers.
¡ Ü Pipelined memory access allows overlapping of memory accesses with execution.
¡ Ü 4KByte on-chip memory.
¡ Ü On-chip instruction cache omits instruction fetch in inner loops and provides pre-fetch.
¡ ÜVariable-length instructions of 16, 32 or 48 bits provide a large, powerful instruction set,
thereby reducing the number of instructions to be executed.
¡ Ü Primarily used 16-bit instructions halve the memory bandwidth required for instruction
fetch in comparison to conventional RISC architectures with fixed-length 32-bit
instructions, yielding also even better code economy than conventional CISC
architectures.
¡ Ü Regular instruction set allows hardwiring of control logic at low component count.
¡ Ü Most instructions execute in one cycle.
¡ Ü Pipelined DSP instructions.
¡ Ü Parallel execution of ALU and DSP instructions.
¡ Ü Single-cycle half word multiply-accumulate operation.
¡ Ü Fast Call and Return by parameter passing via registers.
¡ Ü An instruction pipeline depth of only two stages - decode/execute - provides branching
without insertion of wait cycles in combination with Delayed Branch instructions.
¡ Ü Range and pointer checks are performed without speed penalty, thus, these checks need
no longer be turned off, thereby providing higher runtime reliability.
¡ Ü Separate address and data buses provide a throughput of one 32-bit word each cycle.
The features noted above contribute to reduce the number of idle wait cycles to a bare
minimum. The processor is designed to sustain its execution rate with a standard DRAM
memory.
The low power consumption is of advantage for mobile (portable) applications or in
temperature-sensitive environments.
In the current version, the GMS30C2116 and GMS30C2132 RISC/DSP are implemented in a
0.6 µm-CMOS-process.
The GMS30C2116 and GMS30C2132 RISC/DSP are based on hyperstone architecture.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GMS30C2132.PDF ] | |
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