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PDF GLT5640L32-10 Data sheet ( Hoja de datos )
| Número de pieza | GLT5640L32-10 | |
| Descripción | CMOS Synchronous DRAM 2M x 32 SDRAM | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de GLT5640L32-10 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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G-LINK
ADVANCED
GLT5640L32
CMOS Synchronous DRAM
2M x 32 SDRAM
512K x 32bit x 4Banks
Synchronous DRAM
G-Link Technology Corporation
G-Link Technology Corporation,TaiwanWeb :
www.glink.com.tw Email : [email protected]
TEL : 886-2-26599658
GLINK reserves the right to change products or specification without notice.
G-Link Technology Corp.
1
Dec 2003 Rev.0.3
1 page  
G-LINK
ADVANCED
GLT5640L32
CMOS Synchronous DRAM
PIN DESCRIPTIONS
PIN PIN NAME
CLK System Clock
CKE
CS
BA0, BA1
A0~A10/AP
RAS, CAS, WE
DQM0~3
DQ0~DQ31
VDD / VSS
VDDQ / VSSQ
NC
Clock Enable
Chip select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply/Ground
Data Output Power / Ground
No Connection
DESCRIPTIONS
The system clock input. All other inputs are registered to the
SDRAM on the rising edge CLK
Controls internal clock signal and when deactivated, the
SDRAM will be one of the states among power down,
suspend or self refresh
Enable or disable all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address
Column Address
Auto-precharge flag
: RA0~RA10,
: CA0~CA7,
: A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in
write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
ABSOLUTE MAXIMUM RATING
PARAMETER
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Short Circuit Output Current
Power Dissipation
SYMBOL
TA
TSTG
VIN,VOUT
VDD, VDDQ
IOS
PD
RATING
0~70
-55~125
-1.0~4.6
-1.0~4.6
50
1
UNIT
°C
°C
V
V
mA
W
G-Link Technology Corp.
5
Dec 2003 Rev.0.3
5 Page 
G-LINK
ADVANCED
GLT5640L32
CMOS Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10/AP BA NOTE
Read With Autoprecharge
No Operation
Bank Active
Read
Read With Autoprecharge
Write
Write With Autoprecharge
Precharge All Banks
Precharge Selected Bank
Burst Stop
DQM
Auto Refresh
Entry
Self Refresh
Exit
Precharge
Power Down
Clock Suspend
Exit
Exit
Entry
Exit
H
H
H
H
H
H
H
H
H
H
L
H
L
H
L
X LL L L X
OP Code
-
X LX X X X
LH H H
X
-
X LL H H X
RA V -
X L H L H X CA
LV
H
-
X L H L H X CA
L
HV
-
X LL H L X
X
HX
LV
-
X LH H L X
X
-
X
VX
-
H LL L H X
X
-
L LL L H X
1
H
HX
LH
X
H
X
H
X
X
1
L HX X X X
LH H H
HX X X
H LH H H X
X
-
-
L
HX
LV
X
V
X
V
X
X
-
H XX
-
Notice :
1. Exiting Self Refresh occurs by asynchronously bring CKE from low to high.
2. X = Don’t Care, H = Logic High, L = Logic Low, BA = Bank Address, RA = Row Address, CA = Column Address,
OP Cpde = Operand Code, NOP = No Operation.
G-Link Technology Corp.
11
Dec 2003 Rev.0.3
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GLT5640L32-10.PDF ] | |
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