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PDF ICX274AQ Data sheet ( Hoja de datos )

Número de pieza ICX274AQ
Descripción Diagonal 8.923mm (Type 1/1.8) Progressive Scan CCD Image Sensor
Fabricantes Sony 
Logotipo Sony Logotipo



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ICX274AQ
Diagonal 8.923mm (Type 1/1.8) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX274AQ is a diagonal 8.923mm (Type 1/1.8)
interline CCD solid-state image sensor with a square
pixel array and 2.01M effective pixels. Progressive
scan allows all pixels' signals to be output
independently within approximately 1/15 second,
and output is also possible using various addition
and pulse elimination methods. This chip features an
electronic shutter with variable charge-storage time
which makes it possible to realize full-frame still
images without a mechanical shutter. High resolution
and high color reproductivity are achieved through
the use of R, G, B primary color mosaic filters as the
color filters. Further, high sensitivity and low dark
current are achieved through the adoption of Super
HAD CCD technology.
This chip is suitable for applications such as
electronic still cameras, PC input cameras, etc.
20 pin DIP (Plastic)
Features
High horizontal and vertical resolution
Supports the following modes
Progressive scan mode (with/without mechanical shutter)
2/8-line readout mode
2/4-line readout mode
2-line addition mode
Center scan modes (1), (2) and (3)
AF modes (1) and (2)
Square pixel
Horizontal drive frequency: 28.6364MHz (typ.), 36.0MHz (max.)
Reset gate bias are not adjusted
R, G, B primary color mosaic filters on chip
High sensitivity, low dark current
Continuous variable-speed shutter function
Excellent anti-blooming characteristics
20-pin high-precision plastic package
Pin 1
V
12
Pin 11
H
48
Optical black position
(Top View)
2
10
Device Structure
Interline CCD image sensor
Image size:
Diagonal 8.923mm (Type 1/1.8)
Total number of pixels:
1688 (H) × 1248 (V) approx. 2.11M pixels
Number of effective pixels: 1628 (H) × 1236 (V) approx. 2.01M pixels
Number of active pixels: 1620 (H) × 1220 (V) approx. 1.98M pixels
Recommended number of
recording pixels:
1600 (H) × 1200 (V) approx. 1.92M pixels
Chip size:
8.50mm (H) × 6.80mm (V)
Unit cell size:
4.40µm (H) × 4.40µm (V)
Optical black:
Horizontal (H) direction: Front 12 pixels, rear 48 pixels
Vertical (V) direction: Front 10 pixels, rear 2 pixels
Number of dummy bits: Horizontal 28
Vertical 1
Substrate material:
Silicon
Wfine CCD is trademark of Sony corporation.
Represents a CCD adopting progressive scan, primary color filter and square pixel.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01410D3Z

1 page




ICX274AQ pdf
ICX274AQ
Bias Conditions
Item
Symbol
Min.
Typ.
Max. Unit Remarks
Supply voltage
Protective transistor bias
Substrate voltage No line addition1
adjustment range 2-line addition2
VDD
VL
VSUB
VSUB2
14.55 15.0 15.45
3
Internally generated value
8.8 14.4
V
4
V
Substrate voltage adjustment accuracy
Reset gate clock
VSUB
φRG
Indicated
voltage – 0.2
Indicated
voltage
5
Indicated
voltage + 0.2
V
V
1 Progressive scan mode, 2/8-line readout mode, 2/4-line readout mode, center scan modes (1) and (3),
and AF modes (1) and (2)
2 2-line addition mode and center scan mode (2)
3 VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply
for the V driver should be used.
4 Substrate voltage (VSUB2) setting value indication
The substrate voltage (VSUB) for modes without line addition is generated internally.
The substrate voltage setting value for use with vertical 2-line addition is indicated by a code on the
bottom surface of the image sensor. Adjust the substrate voltage to the indicated voltage.
VSUB2 code – 1-digit indication
VSUB2 code
The code and the actual value correspond as follows.
VSUB2 code 1 2 3 4 6 7 8 9 A C d E f G h
Actual value 8.8 9.0 9.2 9.4 9.6 9.8 10.0 10.2 10.4 10.6 10.8 11.0 11.2 11.4 11.6
VSUB2 code J K L m N P R S U V W X Y Z
Actual value 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 13.4 13.6 13.8 14.0 14.2 14.4
[Example] "h" indicates a VSUB2 setting of 11.6V.
5 Do not apply a DC bias to the reset gate clock pin, because a DC bias is generated within the CCD.
DC characteristics
Item
Supply current
Symbol
IDD
Min.
7.0
Typ.
10.0
Max.
13.0
Unit Remarks
mA
–5–

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ICX274AQ arduino
ICX274AQ
Clock Switching Characteristics (Horizontal drive frequency: 28.6364MHz)
twh twl
tr
tf
Item Symbol
Unit Remarks
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Readout clock VT
3.3 3.5
0.5
0.5
µs
During
readout
Vertical transfer
clock
Horizontal
transfer clock
Vφ1, Vφ4,
Vφ2α, Vφ3α
(α = A to C)
Hφ1β (β = A, B) 10 12.5
Hφ2β (β = A, B) 10 12.5
10 12.5
10 12.5
15 400 ns 1
5 7.5
5 7.5
5
7.5
ns
2
5 7.5
Reset gate clock φRG
47
24
2
3 ns
Substrate clock φSUB
2.1
0.5
0.5
µs
When draining
charge
Item
Horizontal
transfer clock
two
Symbol
Unit Remarks
Min. Typ. Max.
Hφ1A, Hφ1B,
Hφ2A, Hφ2B
8
10
ns
Clock Switching Characteristics (Horizontal drive frequency: 36MHz)
twh twl
tr
tf
Item Symbol
Unit Remarks
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Readout clock VT
4.0 4.2
0.5
0.5
µs
During
readout
Vertical transfer
clock
Horizontal
transfer clock
Vφ1, Vφ4,
Vφ2α, Vφ3α
(α = A to C)
Hφ1β (β = A, B) 8
Hφ2β (β = A, B) 8
9
9
89
89
15 400 ns 1
56
56
5 6 ns 2
56
Reset gate clock φRG
4 5.5
8
2
3 ns
Substrate clock φSUB
1.67
0.25
0.25 µs
When draining
charge
Item
Horizontal
transfer clock
two
Symbol
Unit Remarks
Min. Typ. Max.
Hφ1A, Hφ1B,
Hφ2A, Hφ2B
8
9
ns
1 When two vertical transfer clock drivers CXD3400N are used.
2 tf tr – 2ns, and the cross-point voltage (VCR) for the Hφ1β (β = A, B) rising side of the Hφ1β and Hφ2β
waveforms must be VφH/2 [V] or more.
– 11 –

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