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Número de pieza | V236BJ1-P02 | |
Descripción | TFT LCD Module | |
Fabricantes | CHIMEI Innolux | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de V236BJ1-P02 (archivo pdf) en la parte inferior de esta página. Total 27 Páginas | ||
No Preview Available ! PRODUCT SPECIFICATION
□ Tentative Specification
□ Preliminary Specification
■ Approval Specification
MODEL NO.: V236BJ1
SUFFIX: P02
Customer:
APPROVED BY
SIGNATURE
Name / Title
Note
Please return 1 copy for your confirmation with your signature and
comments.
Approved By
Chao-Chun Chung
Checked By
YP Lee
Prepared By
Wesun Yen
Version 2.1
1
The copyright belongs to InnoLux. Any unauthorized use is prohibited
Date:Jan.31.2013
1 page PRODUCT SPECIFICATION
1.3 MECHANICAL SPECIFICATIONS
Item
Weight
Min.
475
Typ.
490
Max.
505
Unit Note
g-
I/F connector mounting
position
The mounting inclination of the connector makes the
screen center within ± 0.5mm as the horizontal.
(2)
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Connector mounting position
+/- 0.5mm
Version 2.1
5
The copyright belongs to InnoLux. Any unauthorized use is prohibited
Date:Jan.31.2013
5 Page PRODUCT SPECIFICATION
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD OPEN CELL INPUT
CNF1 Connector Pin Assignment P-TWO=187053-30091 or FOXCONN=GS23302-1321S-7H
Pin Name
Description
1
VCC
+12.0V power supply
2
VCC
+12.0V power supply
3
VCC
+12.0V power supply
4
VCC
+12.0V power supply
5
GND
Ground
6
GND
Ground
7
GND
Ground
8 NC No connection
Remark
(2)
9 SELLVDS Select LVDS Format
10 NC NC
11
GND
Ground
12
RX0-
Negative LVDS differential data input. Channel 0
13 RX0+ Positive LVDS differential data input. Channel 0
14
GND
Ground
15
RX1-
Negative LVDS differential data input. Channel 1
16 RX1+ Positive LVDS differential data input. Channel 1
17
GND
Ground
18
RX2-
Negative LVDS differential data input. Channel 2
19 RX2+ Positive LVDS differential data input. Channel 2
20
GND
Ground
21 RXLCK- Negative LVDS differential clock input.
22 RXCLK+ Positive LVDS differential clock input.
23
GND
Ground
24
RX3-
Negative LVDS differential data input. Channel 3
25 RX3+ Positive LVDS differential data input. Channel 3
26
GND
Ground
27 NC No connection
(3)(4)
(2)
(2)
28
SCL
I2C clock (For Vcom tunning)
29
SDA
I2C data (For Vcom tunning)
30
GND
Ground
Note (1) LVDS connector pin orderdefined as below
Note (2) Reserved for internal use. Please leave it open.
Note (3) Connect to Open or +3.3V: VESA Format, connect to GND: JEIDA Format.
SELLVDS
Mode
H(default)
VESA
L JEIDA
L : Connect to GND, H: Connect to +3.3V
Note (4) Interface optional pin has internal scheme as following diagram. Customer should keep the interface voltage level
Version 2.1
11
The copyright belongs to InnoLux. Any unauthorized use is prohibited
Date:Jan.31.2013
11 Page |
Páginas | Total 27 Páginas | |
PDF Descargar | [ Datasheet V236BJ1-P02.PDF ] |
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