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PDF DRX3975D Data sheet ( Hoja de datos )
| Número de pieza | DRX3975D | |
| Descripción | Fourth-Generation COFDM Demodulator | |
| Fabricantes | Micronas | |
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MICRONAS
PRELIMINARY DATA SHEET
DRX 3975D
Fourth-Generation COFDM
Demodulator
Edition Aug. 22, 2005
6251-659-1PD
MICRONAS
1 page  
PRELIMINARY DATA SHEET
DRX 3975D
2.3. AGC
The DRX 3975D provides two AGC control signals,
resulting in two options for tuner and IF control.
2.3.1. Dual AGC
If the system in front of the demodulator consists of
two variable amplifiers, the RF-AGC and IF-AGC sig-
nals are used to control both of them.
2.3.3. AGC TOP setting
When RF AGC signal is used, the RF-AGC should be
programmed so that an optimal setting of the available
amplifiers in the system is chosen. Therefore, a take-
over Point can be defined. The demodulator will
increase the RF gain till the take-over-point (TOP) is
reached. The demodulator uses the sense-input to
measure the energy level. Further amplification is
achieved by increasing the IF gain. A graphical repre-
sentation of this behavior is shown in the following pic-
ture.
RF-AGC
Tuner
IF-AGC
IF in
IF Amp
DRX 3975D
Pre-SAW Sense
Gain
Take Over Point
IF_AGC
RF_AGC
Fig. 2–3: Dual AGC application
2.3.2. IF AGC Only
When using a tuner with closed loop RF AGC, only the
IF-AGC is required to control the IF amplifier.
Tuner
IF-AGC
IF in
IF Amp
DRX 3975D
Fig. 2–5: AGC TOP setting
Input Signal
(dB)
2.4. ADC
The IF input is sampled by a wideband 10 bits ADC.
The clock of the ADC is generated by the integrated
PLL. Additional filtering in front of the ADC is applied to
further improve noise behavior and adjacent channel
performance.
Fig. 2–4: Application with IF AGC only
Micronas
Aug. 22, 2005; 6251-659-1PD
5
5 Page 
PRELIMINARY DATA SHEET
3. Control Interface
3.1. Serial Interface
The DRX 3975D is controlled via an I2C compatible
serial interface. The host application utilizes low-level
read/write I2C functions to control the device driver. A
wide range of I2C access protocols is supported, rang-
ing from a simple 5 Bytes access with no ‘repeated
start’ to more enhanced multiple access modes for
faster control.
DRX 3975D
SDA
Tsu:cond
Tlo:clk Thi:clk
SCL
Tfall
Trise
Thd:cond
Thd:cond
PS
Thd:data
Tsu:data
Tsu:cond
Sr
Fig. 3–1: Serial protocol timing diagram P=Stop, S=Start, Sr=Repeated Start.
Tspike
Tsu:cond
P
Micronas
Aug. 22, 2005; 6251-659-1PD
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DRX3975D.PDF ] | |
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