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Número de pieza XC7VX485T
Descripción Virtex-7 T and XT FPGAs
Fabricantes Xilinx 
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DS183 (v1.21) July 1, 2014
Virtex-7 T and XT FPGAs Data Sheet:
DC and AC Switching Characteristics
Product Specification
Introduction
Virtex®-7 T and XT FPGAs are available in -3, -2, -1, and
-2L speed grades, with -3 having the highest performance.
The -2L devices operate at VCCINT = 1.0V and are screened
for lower maximum static power. The speed specification of
a -2L device is the same as the -2 speed grade. The -2G
speed grade is available in devices utilizing Stacked Silicon
Interconnect (SSI) technology. The -2G speed grade
supports 12.5 Gb/s GTX or 13.1 Gb/s GTH transceivers as
well as the standard -2 speed grade specifications.
Virtex-7 T and XT FPGA DC and AC characteristics are
specified in commercial, extended, industrial, and military
temperature ranges. Except for the operating temperature
range or unless otherwise noted, all the DC and AC
electrical parameters are the same for a particular speed
grade (that is, the timing characteristics of a -1M speed
grade military device are the same as for a -1C speed grade
commercial device). However, only selected speed grades
and/or devices are available in each temperature range.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The
parameters included are common to popular designs and
typical applications.
Available device and package combinations can be found in:
7 Series FPGAs Overview (DS180)
Defense-Grade 7 Series FPGAs Overview (DS185)
This Virtex-7 T and XT FPGA data sheet, part of an overall
set of documentation on the 7 series FPGAs, is available on
the Xilinx website at www.xilinx.com/7.
DC Characteristics
Table 1: Absolute Maximum Ratings(1)
Symbol
Description
FPGA Logic
VCCINT
VCCAUX
VCCBRAM
VCCO
Internal supply voltage
Auxiliary supply voltage
Supply voltage for the block RAM memories
Output drivers supply voltage for 3.3V HR I/O banks
Output drivers supply voltage for 1.8V HP I/O banks
VCCAUX_IO
VREF
Auxiliary supply voltage
Input reference voltage
I/O input voltage for 3.3V HR I/O banks
VIN(2)(3)(4)
I/O input voltage for 1.8V HP I/O banks
I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except
TMDS_33(5)
VCCBATT
Key memory battery backup supply
GTX and GTH Transceivers
VMGTAVCC
VMGTAVTT
VMGTVCCAUX
VMGTREFCLK
Analog supply voltage for the GTX/GTH transmitter and receiver circuits
Analog supply voltage for the GTX/GTH transmitter and receiver termination circuits
Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX/GTH transceivers
GTX/GTH transceiver reference clock absolute input voltage
Min Max Units
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.40
–0.55
–0.40
1.1
2.0
1.1
3.6
2.0
2.06
2.0
VCCO + 0.55
VCCO + 0.55
2.625
V
V
V
V
V
V
V
V
V
V
–0.5 2.0
V
–0.5 1.1
–0.5 1.32
–0.5 1.935
–0.5 1.32
V
V
V
V
© 2011–2014 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Kintex, Artix, Zynq, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in the
United States and other countries. All other trademarks are the property of their respective owners.
DS183 (v1.21) July 1, 2014
Product Specification
www.xilinx.com
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XC7VX485T pdf
Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics
Table 5: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for 1.8V HP I/O Banks(1)(2)
AC Voltage Overshoot
% of UI @–55°C to 125°C AC Voltage Undershoot
% of UI @–55°C to 125°C
VCCO + 0.55
VCCO + 0.60
VCCO + 0.65
VCCO + 0.70
VCCO + 0.75
VCCO + 0.80
VCCO + 0.85
VCCO + 0.90
VCCO + 0.95
100
50.0(3)
50.0(3)
47.0
21.2
9.71
4.51
2.12
1.01
–0.55
–0.60
–0.65
–0.70
–0.75
–0.80
–0.85
–0.90
–0.95
100
50.0(3)
50.0(3)
50.0(3)
50.0(3)
50.0(3)
28.4
12.7
5.79
Notes:
1. A total of 200 mA per bank should not be exceeded.
2. The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND – 0.20V, must not exceed the values
in this table.
3. For UI lasting less than 20 µs.
Table 6: Typical Quiescent Supply Current
Symbol
Description
Device
ICCINTQ
Quiescent VCCINT supply current
XC7V585T
XC7V2000T
XC7VX330T
XC7VX415T
XC7VX485T
XC7VX550T
XC7VX690T
XC7VX980T
XC7VX1140T
XQ7V585T
XQ7VX330T
XQ7VX485T
XQ7VX690T
XQ7VX980T
-3
1483
N/A
1012
1324
1578
2214
2214
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-2G
1483
3756
1012
1324
1578
2214
2214
2580
3448
N/A
N/A
N/A
N/A
N/A
Speed Grade
-2 -2L
1483 1483
3756 3756
1012 1012
1324 1324
1578 1578
2214 2214
2214 2214
2580 2580
3448 3448
1483 1483
1012 1012
1578 1578
2214 N/A
N/A 2580
-1
1483
3756
1012
1324
1578
2214
2214
2580
3448
1483
1012
1578
2214
2580
-1M
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1483
1012
1578
N/A
N/A
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DS183 (v1.21) July 1, 2014
Product Specification
www.xilinx.com
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XC7VX485T arduino
Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics
Table 10: Differential SelectIO DC Input and Output Levels
I/O Standard
VICM(1)
VID(2)
V, Min V, Typ V, Max V, Min V, Typ V, Max
V, Min
VOCM(3)
V, Typ
V, Max
VOD(4)
V, Min V, Typ V, Max
BLVDS_25
0.300 1.200 1.425 0.100 –
1.250
Note 5
MINI_LVDS_25 0.300
PPDS_25
0.200
RSDS_25
0.300
1.200
0.900
0.900
VCCAUX
VCCAUX
1.500
0.200 0.400 0.600
0.100 0.250 0.400
0.100 0.350 0.600
1.000
0.500
1.000
1.200
0.950
1.200
1.400
1.400
1.400
0.300 0.450 0.600
0.100 0.250 0.400
0.100 0.350 0.600
TMDS_33
2.700 2.965 3.230 0.150 0.675 1.200 VCCO–0.405 VCCO–0.300 VCCO–0.190 0.400 0.600 0.800
Notes:
1. VICM is the input common mode voltage.
2. VID is the input differential voltage (Q – Q).
3. VOCM is the output common mode voltage.
4. VOD is the output differential voltage (Q – Q).
5. VOD for BLVDS will vary significantly depending on topology and loading.
6. LVDS_25 is specified in Table 12.
7. LVDS is specified in Table 13.
Table 11: Complementary Differential SelectIO DC Input and Output Levels
I/O Standard
VICM(1)
V, Min V, Typ V, Max
VID(2)
V, Min V, Max
VOL(3)
V, Max
VOH(4)
V, Min
IOL IOH
mA, Max mA, Min
DIFF_HSTL_I
DIFF_HSTL_I_18
DIFF_HSTL_II
DIFF_HSTL_II_18
DIFF_HSUL_12
DIFF_MOBILE_DDR
DIFF_SSTL12
DIFF_SSTL135
DIFF_SSTL135_R
DIFF_SSTL15
DIFF_SSTL15_R
DIFF_SSTL18_I
DIFF_SSTL18_II
0.300
0.300
0.300
0.300
0.300
0.300
0.300
0.300
0.300
0.300
0.300
0.300
0.300
0.750
0.900
0.750
0.900
0.600
0.900
0.600
0.675
0.675
0.750
0.750
0.900
0.900
1.125
1.425
1.125
1.425
0.850
1.425
0.850
1.000
1.000
1.125
1.125
1.425
1.425
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.400
VCCO–0.400
8.00 –8.00
0.400
VCCO–0.400
8.00 –8.00
0.400
VCCO–0.400
16.00 –16.00
0.400
VCCO–0.400
16.00 –16.00
20% VCCO
80% VCCO
0.100 –0.100
10% VCCO
90% VCCO
0.100 –0.100
– (VCCO/2) – 0.150 (VCCO/2) + 0.150 14.25 –14.25
– (VCCO/2) – 0.150 (VCCO/2) + 0.150 13.0
–13.0
– (VCCO/2) – 0.150 (VCCO/2) + 0.150 8.9
–8.9
– (VCCO/2) – 0.175 (VCCO/2) + 0.175 13.0
–13.0
– (VCCO/2) – 0.175 (VCCO/2) + 0.175 8.9
–8.9
– (VCCO/2) – 0.470 (VCCO/2) + 0.470 8.00
–8.00
– (VCCO/2) – 0.600 (VCCO/2) + 0.600 13.4
–13.4
Notes:
1. VICM is the input common mode voltage.
2. VID is the input differential voltage (Q – Q).
3. VOL is the single-ended low-output voltage.
4. VOH is the single-ended high-output voltage.
DS183 (v1.21) July 1, 2014
Product Specification
www.xilinx.com
Send Feedback
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