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PDF R5F10EGEAFB Data sheet ( Hoja de datos )

Número de pieza R5F10EGEAFB
Descripción Combines Multi-channel 12-Bit A/D Converter
Fabricantes Renesas Technology 
Logotipo Renesas Technology Logotipo



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No Preview Available ! R5F10EGEAFB Hoja de datos, Descripción, Manual

Preliminary Datasheet
Specifications in this document are tentative and subject to change.
RL78/G1A
R01DS0151EJ0001
RENESAS MCU
Rev.0.01
2011.12.26
Combines Multi-channel 12-Bit A/D Converter, True Low Power Platform (as low as 66 µA/MHz, and
0.57 µA for RTC + LVD), 1.6 V to 3.6 V operation, 16 to 64 Kbyte Flash, 41 DMIPS at 32 MHz
1. OUTLINE
1.1 Features
Ultra-Low Power Technology
1.6 V to 3.6 V operation from a single supply
Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31
µA
Halt (RTC + LVD): 0.57 µA
Snooze: T.B.D.
Operating: 66 µA/MHz
16-bit RL78 CPU Core
Delivers 41 DMIPS at maximum operating frequency
of 32 MHz
Instruction Execution: 86% of instructions can be
executed in 1 to 2 clock cycles
CISC Architecture (Harvard) with 3-stage pipeline
Multiply Signed & Unsigned: 16 x 16 to 32-bit result in
1 clock cycle
MAC: 16 x 16 to 32-bit result in 2 clock cycles
16-bit barrel shifter for shift & rotate in 1 clock cycle
1-wire on-chip debug function
Code Flash Memory
Density: 16 KB to 64 KB
Block size: 1 KB
On-chip single voltage flash memory with protection
from block erase/writing
Self-programming with secure boot swap function
and flash shield window function
Data Flash Memory
Data Flash with background operation
Data flash size: 4 KB
Erase Cycles: 1 Million (typ.)
Erase/programming voltage: 1.8 V to 3.6 V
RAM
2 KB to 4 KB size options
Supports operands or instructions
Back-up retention in all modes
High-speed On-chip Oscillator
32 MHz with +/1% accuracy over voltage (1.8 V to
3.6 V) and temperature (20 °C to +85 °C)
Pre-configured settings: 32 MHz, 24 MHz, 16 MHz,
12 MHz, 8 MHz, 4 MHz & 1 MHz
Reset and Supply Management
Power-on reset (POR) monitor/generator
Low voltage detection (LVD) with 12 setting options
(Interrupt and/or reset function)
Data Memory Access (DMA) Controller
Up to 2 fully programmable channels
Transfer unit: 8- or 16-bit
Multiple Communication Interfaces
Up to 6 x I2C master
Up to 1 x I2C multi-master
Up to 6 x CSI/SPI (7-, 8-bit)
Up to 3 x UART (7-, 8-, 9-bit)
Up to 1 x LIN
Extended-Function Timers
Multi-function 16-bit timers: Up to 8 channels
Real-time clock (RTC): 1 channel (full calendar and
alarm function with watch correction function)
Interval Timer: 12-bit, 1 channel
15 kHz watchdog timer: 1 channel (window function)
Rich Analog
ADC: Up to 28 channels, 12-bit resolution, 3.375 µs
conversion time
Supports 1.6 V
Internalwww.DataSheet.net/ voltage reference (1.45 V)
On-chip temperature sensor
Safety Features (IEC or UL 60730 compliance)
Flash memory CRC calculation
RAM parity error check
RAM write protection
SFR write protection
Illegal memory access detection
Clock stop/ frequency detection
ADC self-test
General Purpose I/O
3.6 V tolerant, high-current (up to 20 mA per pin)
Open-Drain, Internal Pull-up support
Operating Ambient Temperature
Standard: 40 °C to +85 °C
Package Type and Pin Count
From 3 mm x 3 mm to 10 mm x 10 mm
QFP: 48, 64
QFN: 32, 48
LGA: 25
BGA: 64
R01DS0151EJ0001 Rev.0.01
2011.12.26
Page 1 of 76
Datasheet pdf - http://www.DataSheet4U.co.kr/

1 page




R5F10EGEAFB pdf
Under development
RL78/G1A
Preliminary document
Specifications in this document are tentative and subject to change.
1.3.2 32-pin products
32-pin plastic WQFN (fine pitch) (5 × 5)
1. OUTLINE
P24/ANI4/(KR5)
P23/ANI3/(KR4)
P22/ANI2/(KR3)
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P03/ANI16/RxD1/TO00/(KR2)
P02/ANI17/TxD1/TI00/(KR1)
P120/ANI19/(KR0)
24 23 22 21 20 19 18 17
25 16
26 15
27 14
28 13
29 12
30 11
31 10
32 9
123456 78
www.DataSheet.net/
exposed die pad
P51/SO11/INTP2
P50/ANI26/SI11/SDA11/INTP1
P30/ANI27/SCK11/SCL11/INTP3
P70/ANI28/KR0
P31/ANI29/TI03/TO03/PCLBUZ0/INTP4
P62
P61/SDAA0
P60/SCLA0
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0151EJ0001 Rev.0.01
2011.12.26
Page 5 of 76
Datasheet pdf - http://www.DataSheet4U.co.kr/

5 Page





R5F10EGEAFB arduino
Under development
RL78/G1A
Preliminary document
Specifications in this document are tentative and subject to change.
1.5 Block Diagram
1. OUTLINE
1.5.1 25-pin products
TI00/P02
TO00/P03
TI03/TO03/P31
TIMER ARRAY
UNIT (8ch)
ch0
ch1
ch2
ch3
ch4
ch5
ch6
ch7
RxD0/P11
TxD0/P12
RxD1/P03
TxD1/P02
SCK00/P10
SI00/P11
SO00/P12
SCK11/P30
SI11/P50
SO11/P51
SCL00/P10
SDA00/P11
SCL11/P30
SDA11/P50
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
UART0
UART1
CSI00
CSI11
IIC00
IIC11
DIRECT MEMORY
ACCESS CONTROL
BCD
ADJUSTMENT
KEY
RETURN
KR0/P02
KR1/P03
KR2/P22
KR3/P23
INTERVAL
TIMER
RL78
CPU
CORE
CODE FLASH MEMORY
DATA FLASH MEMORY
RAM
www.DataSheet.net/
VDD VSS TOOLRxD/P11,
AVDD AVSS TOOLTxD/P12
SERIAL
INTERFACE IICA0
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
MULTIPLIER&
DIVIDER,
MULITIPLY-
ACCUMULATOR
SDAA0/P61
SCLA0/P60
PCLBUZ0/P31
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
2 P02, P03
3 P10 to P12
4 P20 to P23
2 P30, P31
P40
2 P50, P51
2 P60, P61
PORT 12
2 P121, P122
PORT 13
P137
(KEY RETURN)
(4)
(KR0/P02, KR1/P03,
KR2/P22, KR3/P23)
A/D CONVERTER
4
ANI0/P20 to
ANI3/P23
9
ANI16/P03, ANI17/P02,
ANI18/P10, ANI20/P11,
ANI21/P12, ANI25/P51,
ANI26/P50, ANI27/P30,
ANI29/P31
AVREFP/P20
AVREFM/P21
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
ON-CHIP DEBUG
TOOL0/P40
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
VOLTAGE
REGULATOR
INTERRUPT
CONTROL
RESET
X1/P121
X2/EXCLK/P122
REGC
INTP0/P137
INTP1/P50
INTP2/P51
2
INTP3/P30,
INTP4/P31
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0151EJ0001 Rev.0.01
2011.12.26
Page 11 of 76
Datasheet pdf - http://www.DataSheet4U.co.kr/

11 Page







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