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PDF M170E1-04 Data sheet ( Hoja de datos )
| Número de pieza | M170E1-04 | |
| Descripción | TFT LCD Module | |
| Fabricantes | CHIMEI | |
| Logotipo |  |
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GENERAL DESCRIPTION
Issue Date: June.01’2001
Model: M170E1 -04
Approval
OVERVIEW
This product is a 17.0” TFT Liquid Crystal Display Module with 2 dual CCFLs Backlight unit and 30 pins
LVDS interface. This module supports 1280 x 1024 SXGA mode and can display 16 million colors. The
inverter module for Backlight is not built in.
FEATURES
-SXGA (1280x1024 pixels) resolution
-2 dual CCFLs (Cold Cathode Fluorescent Lamp)
-DE only Mode
-LVDS (Low Voltage Differential Signaling) Interface
APPLICATION
-TFT-LCD Monitor
GENERAL SPECIFICATI0NS
Item
Screen Size
Bezel Opening Area
Effective Display Area
Driver Element
Pixel Number
Pixel Pitch
Pixel Arrangement
Display Colors
Transmissive Mode
Surface Treatment
Spec.
17.0 Diagonal
342.0(H) x 274.4(V)
337.92(H) x 270.34(V)
a-si TFT active matrix
1280 x R.G.B. x 1024
0.264(H) x 0.264(W)
RGB vertical stripe
16M
Normally White
Haze 25%,Hard-Coating,Anti-static
MECHANICAL SPECIFICATIONS
Item
Horizontal(H)
Module Size Vertical(V)
Depth(D)
Min.
403.5
321.7
-
Weight
-
Typ.
404
322.2
-
2,000
Max.
404.5
322.7
21
2,150
Unit
inch
mm
mm
-
pixel
mm
-
color
-
-
Unit
mm
mm
mm
g
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Issue Date: June.01’2001
Model: M170E1 -04
Approval
4. INTERFACE SPECIFICATIONS
4.1 THE LVDS INTERFACE SIGNAL DESCRIPTION
Pin Name
1 VCC
2 VCC
3 VCC
4 GND
5 GND
6 GND
7 SELLVDS
8 TEST
9 GND
10 RXO3+
11 RXO3-
12 RXOC+
13 RXOC-
14 RXO2+
15 RXO2-
16 RXO1+
17 RXO1-
18 RXO0+
19 RXO0-
20 RXE3+
21 RXE3-
22 RXEC+
23 RXEC-
24 RXE2+
25 RXE2-
26 RXE1+
27 RXE1-
28 RXE0+
29 RXE0-
30 GND
Description
+5.0V power supply
+5.0V power supply
+5.0V power supply
Ground
Ground
Ground
Select LVDS data order. Connect this pin to low. See the following table.
Test pin should be tied to ground.
Ground
Positive LVDS differential data input. Channel O3 (odd)
Negative LVDS differential data input. Channel O3(odd)
Positive LVDS differential clock input. (odd)
Negative LVDS differential clock input. (odd)
Positive LVDS differential data input. Channel O2 (odd)
Negative LVDS differential data input. Channel O2 (odd)
Positive LVDS differential data input. Channel O1 (odd)
Negative LVDS differential data input. Channel O1 (odd)
Positive LVDS differential data input. Channel O0 (odd)
Negative LVDS differential data input. Channel O0 (odd)
Positive LVDS differential data input. Channel E3 (even)
Negative LVDS differential data input. Channel E3 (even)
Positive LVDS differential clock input. (even)
Negative LVDS differential clock input. (even)
Positive LVDS differential data input. Channel E2 (even)
Negative LVDS differential data input. Channel E2 (even)
Positive LVDS differential data input. Channel E1 (even)
Negative LVDS differential data input. Channel E1 (even)
Positive LVDS differential data input. Channel E0 (even)
Negative LVDS differential data input. Channel E0 (even)
Ground
Note (1) Connector Part No.: FI-SE30P-HF (JAE)
Note (2) The first pixel is even.
Note (3) Input signal of even and odd clock should be the same timing.
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| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet M170E1-04.PDF ] | |
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