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PDF V390HJ1-P01 Data sheet ( Hoja de datos )

Número de pieza V390HJ1-P01
Descripción TFT LCD Module
Fabricantes ChiMei 
Logotipo ChiMei Logotipo



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Global LCD Panel Exchange Center
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PRODUCT SPECIFICATION
Ƒ Tentative Specification
Ƒ Preliminary Specification
Ŷ Approval Specification
MODEL NO.: V390HJ1
SUFFIX: P01
Customer:
APPROVED BY
Name / Title
Note
SIGNATURE
Please return 1 copy for your confirmation with your signature and
comments.
Approved By
Checked By Prepared By
Chao-Chun Chung Roger Huang WJ Chang
Version 2.0
1 DateΚ23 Nov. 2011
The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com

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V390HJ1-P01 pdf
Global LCD Panel Exchange Center
www.panelook.com
PRODUCT SPECIFICATION
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item
Storage Temperature
Operating Ambient Temperature
Symbol
TST
TOP
Value
Min. Max.
-20 +60
0 50
Note (1) Temperature and relative humidity range is shown in the figure below.
Unit Note
ºC (1)
ºC (1), (2)
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature
of display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Relative Humidity (%RH)
100
90
80
60
Operating Range
40
20
10 Storage Range
-40 -20
0 20 40
Temperature (ºC)
60 80
Version 2.0
5 DateΚ23 Nov. 2011
The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com

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V390HJ1-P01 arduino
Global LCD Panel Exchange Center
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PRODUCT SPECIFICATION
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE INPUT
CNF1 Connector Pin Assignment: (FI-RE51S-HF(JAE) or equivalent)
Pin Name
1 GND
2 N.C.
3 N.C.
4 N.C.
5 N.C.
6 N.C.
7 SELLVDS
8 N.C.
9 N.C
10 N.C.
11 GND
12 ERX0-
13 ERX0+
14 ERX1-
15 ERX1+
16 ERX2-
17 ERX2+
18 GND
19 ECLK-
20 ECLK+
21 GND
22 ERX3-
23 ERX3+
24 N.C.
25 N.C.
26 GND
27 GND
28 ORX0-
29 ORX0+
30 ORX1-
31 ORX1+
32 ORX2-
33 ORX2+
34 GND
35 OCLK-
36 OCLK+
37 GND
38 ORX3-
39 ORX3+
40 N.C.
41 N.C.
42 GND
43 GND
44 GND
45 GND
46 GND
47 N.C.
48 VCC
49 VCC
50 VCC
51 VCC
Description
Ground
No Connection
No Connection
No Connection
No Connection
No Connection
LVDS data format Selection
No Connection
No Connection
No Connection
Ground
Even pixel Negative LVDS differential data input. Channel 0
Even pixel Positive LVDS differential data input. Channel 0
Even pixel Negative LVDS differential data input. Channel 1
Even pixel Positive LVDS differential data input. Channel 1
Even pixel Negative LVDS differential data input. Channel 2
Even pixel Positive LVDS differential data input. Channel 2
Ground
Even pixel Negative LVDS differential clock input.
Even pixel Positive LVDS differential clock input.
Ground
Even pixel Negative LVDS differential data input. Channel 3
Even pixel Positive LVDS differential data input. Channel 3
No Connection
No Connection
Ground
Ground
Odd pixel Negative LVDS differential data input. Channel 0
Odd pixel Positive LVDS differential data input. Channel 0
Odd pixel Negative LVDS differential data input. Channel 1
Odd pixel Positive LVDS differential data input. Channel 1
Odd pixel Negative LVDS differential data input. Channel 2
Odd pixel Positive LVDS differential data input. Channel 2
Ground
Odd pixel Negative LVDS differential clock input
Odd pixel Positive LVDS differential clock input
Ground
Odd pixel Negative LVDS differential data input. Channel 3
Odd pixel Positive LVDS differential data input. Channel 3
No Connection
No Connection
Ground
Ground
Ground
Ground
Ground
No Connection
Power input (+12V)
Power input (+12V)
Power input (+12V)
Power input (+12V)
Note (1) LVDS connector pin order defined as follows
Note
(2)
(3)(4)
(2)
(2)
(2)
(5)
(5)
(5)
(2)
(5)
(5)
(5)
(2)
(2)
Version 2.0
11 DateΚ23 Nov. 2011
The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com

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