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PDF STU7N80K5 Data sheet ( Hoja de datos )

Número de pieza STU7N80K5
Descripción N-channel Power MOSFET
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! STU7N80K5 Hoja de datos, Descripción, Manual

STD7N80K5, STP7N80K5,
STU7N80K5
N-channel 800 V, 0.95 Ω typ., 6 A Zener-protected SuperMESH™ 5
Power MOSFETs in DPAK, TO-220 and IPAK packages
Datasheet - production data
TAB
23
1
DPAK
TAB
TAB
3
2
1
TO-220
IPAK
3
2
1
Features
Order codes
STD7N80K5
STP7N80K5
STU7N80K5
VDS
800 V
RDS(on)max
1.2 Ω
ID PTOT
6 A 110 W
Worldwide best FOM (figure of merit)
Ultra low gate charge
100% avalanche tested
Zener-protected
Figure 1. Internal schematic diagram
D(2, TAB)
Applications
Switching applications
G(1)
S(3)
AM01476v1
Description
These N-channel Zener-protected Power
MOSFETs are designed using ST’s revolutionary
avalanche-rugged very high voltage
SuperMESH™ 5 technology, based on an
innovative proprietary vertical structure. The
result is a dramatic reduction in on-resistance,
and ultra-low gate charge for applications which
require superior power density and high
efficiency.
Order codes
STD7N80K5
STP7N80K5
STU7N80K5
Table 1. Device summary
Marking
Package
7N80K5
DPAK
TO-220
IPAK
Packaging
Tape and reel
Tube
October 2013
This is information on a product in full production.
DocID023448 Rev 5
1/21
www.st.com

1 page




STU7N80K5 pdf
STD7N80K5, STP7N80K5, STU7N80K5
Electrical characteristics
Table 6. Switching times
Symbol
Parameter
Test conditions
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
VDD = 400 V, ID = 3 A,
RG=4.7 Ω, VGS=10 V
(see Figure 19)
Min. Typ. Max. Unit
- 11.3 -
8.3
23.7
20.2
ns
ns
ns
ns
Table 7. Source drain diode
Symbol
Parameter
Test conditions
ISD Source-drain current
ISDM
VSD(1)
Source-drain current (pulsed)
Forward on voltage
ISD= 6 A, VGS=0
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD= 6 A, VDD= 60 V
di/dt = 100 A/µs,
(see Figure 18)
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD= 6 A,VDD= 60 V
di/dt=100 A/µs,
Tj=150 °C
(see Figure 18)
1. Pulsed: pulse duration = 300µs, duty cycle 1.5%
Min. Typ. Max. Unit
- 6A
- 24 A
- 1.5 V
- 315
ns
- 2.8
µC
- 17.5
A
- 480
ns
- 3.8
µC
- 16
A
Table 8. Gate-source Zener diode
Symbol
Parameter
Test conditions
Min Typ. Max Unit
V(BR)GSO Gate-source breakdown voltage IGS= ± 1mA, ID=0
30 - - V
The built-in back-to-back Zener diodes have been specifically designed to enhance not only
the device's ESD capability, but also to make them capable of safely absorbing any voltage
transients that may occasionally be applied from gate to source. In this respect, the Zener
voltage is appropriate to achieve efficient and cost-effective protection of device integrity.
The integrated Zener diodes thus eliminate the need for external components.
DocID023448 Rev 5
5/21
21

5 Page





STU7N80K5 arduino
STD7N80K5, STP7N80K5, STU7N80K5
Package mechanical data
Dim.
A
A1
A2
b
b4
c
c2
D
D1
E
E1
e
e1
H
L
(L1)
L2
L4
R
V2
Table 9. DPAK (TO-252) type A mechanical data
mm
Min.
2.20
0.90
0.03
0.64
5.20
0.45
0.48
6.00
6.40
4.40
9.35
1.00
0.60
Typ.
5.10
4.70
2.28
2.80
0.80
0.20
Max.
2.40
1.10
0.23
0.90
5.40
0.60
0.60
6.20
6.60
4.60
10.10
1.50
1.00
DocID023448 Rev 5
11/21
21

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