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PDF SM7301 Data sheet ( Hoja de datos )

Número de pieza SM7301
Descripción Specification of Programming FLASH
Fabricantes SyncMOS 
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SH 1 OF 1
Specification of Programming FLASH
SM7301
1. General Description
The SM7301 is normally shipped with the on-chip FLASH memory array in the erased state (that is, contents = FFH) and ready to be programmed. To programming on-chip
FLASH memory, MCU must be in the RESET mode.
2. Pin Assignment and Description
40 Pins DIP
44 Pins QFP
44 Pins PLCC
Name
I/O Description
1,2,3,4,5,6,7,8
40,41,42,43,44,1,2,3
2,3,4,5,6,7,8,9
P1 I The low-byte of address (A7-A0), *1
21,22,23,24,25
18,19,20,21,22
24,25,26,27,28
P2 I The high-byte of address (A12-A8) *1
26,27,28
23,24,25
29,30,31
TST[1:3]
I
Test pin must connect to 0V
32,33,34,35,36,37,38,39 30,31,32,33,34,35,36,37 36,37,38,39,40,41,42,43
P0
I/O The data bus (D7 – D0)
94
10
RES I Reset pin, must be in 5V when programming
FLASH
19 15
21
X1 I Crystal in, feed clock into the MCU
31 29
35
EA I +11.2V voltage supply in ERASE and
PROGRAMMING
40 38
44
VDD
I +5V voltage supply.
20 16
22
VSS I Sink voltage, Ground
30 27
33
ALE I Flash chip enable
29 26
32
PSEN I Flash data output enable
10 5
11
P3.0 I Enable Chip-Erase Mode (low active)
13 9
15
P3.3 I Enable Programming Mode (low active)
14 10
16
P3.4 I Enable Programming Protect bit (low active)
15 11
17
P3.5 I Enable Flash Mode Select
11,12
7,8
13,14
P3.1,P3.2
I
Must set the HIGH, When enter Programming
FLASH
18 14
20
X2 O Crystal out, Let floating
16, 17,
12,13
18,19
P3.6, P3.7
O
Let all unused pins are floating.
17,28,39,6
23,34,1,12
P4 O Let all unused pins are floating.
*1 The size of FLASH RAM in SM7301 is 8K bytes. So the address (P2.7-P2.0 P1.7-P1.0) is from 0x0000 to 0x1FFF.
本資料所有權屬新茂國際科技股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式°
ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION.
表單編號:

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SM7301 pdf
SH 5 OF 5
Symbol
1/Tclc
Tdrst
Tdpwr
Tdea
Tsmod
Tprot
Thmod1
Thmod2
Thea
Tfea
Thpwr
Min
1
4096
10
10
5
200
5
1
1
10
1
Typ
Max Units Description
12 MHz The frequency feed into X1 Pin
Tclc Wait for timer of reset
ms Delay for waiting the stable power(5V)
ms Delay for waiting the stable power(11.2V)
us Setup timing from change of mode pins (P3.0-P3.5) to ALE
us Timing of programming PROTECT bit
us Hold time form falling edge of ALE to falling edge of P3.0-P3.4
5 us Hold time from rising edge of ALE to P3.5
us Hold time form model change to release EA (from 11.2V to 5V)
ms Hold time for change internal voltage from high (11.2) to 5V
us Timing between falling edge of VCC (+5V) and falling edge of all other pins.
5.3. Verified Mode
VCC
RES
X1
EA
PSEN
ALE
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
Tdpwr
Tdrst
P0[7:0]
P1[7:0] 00
P2[7:0] 00
floating
FF
FF
Tspsen
Thpsen
D(n)
n
n
Tdout
D(m)
m
m
Thdout
D(x)
x
x
D(y)
y
y
Thpwr
floating
00
00
本資料所有權屬新茂國際科技股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式°
ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION.
表單編號:

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