|
|
PDF 25Q80BSIG Data sheet ( Hoja de datos )
| Número de pieza | 25Q80BSIG | |
| Descripción | Dual and Quad Serial Flash | |
| Fabricantes | GigaDevice | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 25Q80BSIG (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
25Q80BSIG
FEATURES
◆ 8M-bit Serial Flash
-1024K-byte
-256 bytes per programmable page
◆ Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆ High Speed Clock Frequency
-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 180Mbits/s
-Quad I/O Data transfer up to 360Mbits/s
◆ Program/Erase Speed
-Page Program time: 0.7ms typical
-Sector Erase time: 100ms typical
-Block Erase time: 0.3/0.4/0.8s typical
-Chip Erase time: 8s typical
◆ Flexible Architecture
-Sector of 4K-byte
-Block of 32/64/128K-byte
◆ Low Power Consumption
-20mA maximum active current
-5uA maximum power down current
◆ Software/Hardware Write Protection
-Write protect all/portion of memory via software
-Enable/Disable protection with WP# Pin
-Top or Bottom, Sector or Block selection
◆ Minimum 100,000 Program/Erase Cycles
Note: 1.Please contact Gigadevice for details
◆ Advanced security Features(1)
-16-Bit Customer ID
-Security Architecture
◆ Single Power Supply Voltage
-Full voltage range:2.7~3.6V
http://www.DataSheet4U.net/
GENERAL DESCRIPTION
The GD25Q80 (8M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 180Mbits/s and the Quad I/O & Quad output data is transferred with speed of
360Mbits/s.
CONNECTION DIAGRAM
CS# 1
8
SO
WP#
27
Top View
36
VSS
45
8–LEAD SOP/DIP
VCC
HOLD#
SCLK
SI
1
datasheet pdf - http://www.DataSheet4U.net/
1 page  
Uniform Sector
Dual and Quad Serial Flash
GD25Q80
Data Protection
The GD25Q80 provide the following data protection methods:
◆ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:
-Power-Up
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE)
-Block Erase (BE)
-Chip Erase (CE)
◆ Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the memory
array that can be read but not change.
◆ Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
◆ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down Mode command.
Table1. GD25Q80 Protected area size
Status Register Content
Memory Content
BP4 BP3 BP2 BP1 BP0
XX0 0 0
Blocks
NONE
Addresses
NONE
Density
NONE
Portion
NONE
00001
15
0F0000H-0FFFFFH
64KB
Upper 1/16
0 0 0 1 0 14 to 15
0E0000H-0FFFFFHhttp://www.DataSheet4U.net/
128KB
Upper 1/8
0 0 0 1 1 12 to 15
0C0000H-0FFFFFH
256KB
Upper 1/4
0 0 1 0 0 8 to 15
080000H-0FFFFFH
512KB
Upper 1/2
01001
0
000000H-00FFFFH
64KB
Lower 1/16
01010
0 to 1
000000H-01FFFFH
128KB
Lower 1/8
01011
0 to 3
000000H-03FFFFH
256KB
Lower 1/4
01100
0 to 7
000000H-07FFFFH
512KB
Lower 1/2
0 X 1 0 1 0 to 15
000000H-0FFFFFH
1M
ALL
X X 1 1 X 0 to 15
000000H-0FFFFFH
1M
ALL
10001
15
0FF000H-0FFFFFH
4KB Top Block
10010
15
0FE000H-0FFFFFH
8KB Top Block
10011
15
0FC000H-0FFFFFH
16KB
Top Block
1010X
15
0F8000H-0FFFFFH
32KB
Top Block
11001
0
000000H-000FFFH
4KB Bottom Block
11010
0
000000H-001FFFH
8KB Bottom Block
11011
0
000000H-003FFFH
16KB
Bottom Block
1110X
0
000000H-007FFFH
32KB
Bottom Block
5
datasheet pdf - http://www.DataSheet4U.net/
5 Page 
Uniform Sector
Dual and Quad Serial Flash
GD25Q80
Read Data Bytes At Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte
address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content,
at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The
first byte addressed can be at any location. The address is automatically incremented to the next higher address after each
byte of data is shifted out.
Figure7. Read Data Bytes at Higher Speed Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Command
24-bit address
SI
0BH
23 22 21
3210
SO
CS#
SCLK
SI
SO
High-Z
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
76543210
Data Out1
Data Out2
76543210765
MSB
http://www.DataSheet4U.net/
MSB
Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure8. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure8. Dual Output Fast Read Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
SI
SO
CS#
SCLK
SI
SO
Command
3BH
High-Z
24-bit address
23 22 21
3210
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
642064206
Data Out1 Data Out2
75317531 7
MSB
MSB
11
datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 25Q80BSIG.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 25Q80BSIG | Dual and Quad Serial Flash | GigaDevice |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |