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PDF FD1771-01 Data sheet ( Hoja de datos )

Número de pieza FD1771-01
Descripción FLOPPY DISK FORMATTER/CONTROLlER
Fabricantes Western Digital 
Logotipo Western Digital Logotipo



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WESTERN DIGITAL
COR PO RAT /0 N
FD1771-01 Floppy Disk Formatter/Controller
FEATURES
• SOFT SECTOR FORMAT COMPATIBILITY
• AUTOMATIC TRACK SEEK WITH VERIFICATION
• READ MODE
Single/Multiple Sector Write with Automatic
Sector Search or Entire Track Read
Selectable 128 Byte or Variable Length Sector
• WRITE MODE
Single/Multiple Sector Write with Automatic
Sector Search
Entire Track Write for Diskette Formatting
• PROGRAMMABLE CONTROLS
Selectable Track-to-Track Stepping Time
Selectable Head Settling and Head Engage
Times
Selectable Three Phase or Step and Direction
and Head Positioning Motor Controls
• SYSTEM COMPATIBILITY
i
Double Buffering of Data a-Bit Bi-Directional ....
Bus for Data. Control and Status
DMA or Programmed Data Transfers
All Inputs and Outputs are TTL Compatible
.,uzi
;:)
APPLICATIONS
• FLOPPY DISK DRIVE INTERFACE
• SINGLE OR MULTIPLE DRIVE
CONTROLLER/FORMATTER
• NEW MINI-FLOPPY CONTROLLER
GENERAL DESCRIPTION
The FD1771 is a MOS/LSI device that performs the
functions of a Floppy Disk Controller/Formatter.
The device is designed to be included in the disk
drive electronics, and contains a flexible interface
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1 page




FD1771-01 pdf
Arithmetic/Logic Unit (ALU): The ALU is a serial
comparator, incrementer, and decrementer and is
used for register modification and comparisons with
the disk recorded 10 field.
AM Detector: The Address Mark detector is used to
detect 10, Data, and Index address marks during
Read and Write operations.
Timing and Control: All computer and Floppy Disk
Interface controls are generated through this logic.
The internal device timing is generated from a 2.0
MHz external crystal clock.
PROCESSOR INTERFACE
The interface to the processor is accomplished
through the eight Data Access Lines (DAL) and
associated control signals. The DAL are used to
transfer Data, Status, and Control words out of, or
into the FD1771. The DAL are three-state buffers that
are enabled as output drive~s when Chip Select (CS)
and Read Enable (RE) are active (low logic state) or
act as input receivers when CS and Write Enable
(WE) are active.
When transfer of data with the Floppy Disk Con-
troller is required by the host processor, the device
address is decoded and CS is made low. The least-
significant address bits A 1 and AO, combined with
the signals RE during a Read operation or WE during
a Write operation are interpreted as selecting the fol-
lowing registers:
A1-AO READ (RE)
o 0 Status Register
o 1 Track Register
1 0 Sector Register
1 1 Data Register
WRITE (WE)
Command Register
Track Register
Sector Register
Data Register
During Direct Memory Access (DMA) types of data
transfers between the Data Register of the FD1771
and the Processor, the Data Request (DRQ) output is
used in Data Transfer control. This signal also
appears as status bit 1 during Read and Write
operations.
On Disk Read operations the Data Request is acti-
vated (set high) when an assembled serial input byte
is transferred in parallel to the Data Register. This bit
is cleared when the Data Register is read by the pro-
cessor. If the Data Register is read after one or more
characters are lost, by having new data transferred
into the register prior to processor readout, the Lost
Data bit is set in the Status Register. The Read opera-
tion continues until the end of sect()r is reached.
On Disk Write operations the Data Request is acti-
vated when the Data Register transfers its contents
to the Data Shift Register, and requires a new data
byte. It is reset when the Data Register is loaded with
new data by the processor. If new data is not loaded
at the time the next serial byte is required by the
Floppy Disk, a byte of zeroes is written on the
diskette and the Lost Data bit is set in the Status
Register.
The Lost Data bit and certain other bits in the Status
Register will activate the interrupt request (INTRQ).
The interrupt line is also activated with normal com-
pletion or abnormal termination of all controller
operations. The INTRQ signal remains active until
reset by reading the Status Register to the processor
or by the loading of the Command Register. In addi-
tion, the INTRQ is generated if a Force Interrupt
command condition is met.
FLOPPY DISK INTERFACE
The Floppy Disk interface consists of head position-
ing controls, write gate controls, and data transfers.
A 2.0 MHz ± 1% square wave clock is requred at the
ClK input for internal control timing (may be 1.0
MHz for mini floppy).
HEAD POSITIONING
Four commands cause positioning of the Read-
Write head (see Command Section). The period of
each positioning step is specified by the rfield in bits
1 and 0 of the command word. After the last direc-
tional step, an additional 10 milliseconds of head set-
tling time takes place. The four programmable
stepping rates are tabulated below.
The rates (shown in Table 1) can be applied to a
Three-Phase Motor or a Step-Direction Motor through
the device interface. When the 3m input is con-
nected to ground, the device operates with a three-
phase motor control interface, with one active low
signal per phase on the three output signals PH1,
PH2, and PH3. The stepping sequence, when step-
ping in, is Phases 1-2-3-1, and when stepping out,
Phases 1-3-2-1. Phase 1 is active low after Master
Reset. Note: PH3 needs an inverter if used.
The Step-Direction Motor Control interface is acti-
vated by leaving input 3PM open or connecting it to
+5V. The Phase 1 pin PH1 becomes a Step pulse of 4
microseconds width. The Phase 2 pin PH2 becomes
a direction control with a high voltage on this pin
indicating a Step In, and a low voltage indicating a
Step Out. The Direction output is valid a minimum of
24 J.lS prior to the activation of the Step pulse.
When a Seek, Step or Restore command is executed,
an optional verification of Read-Write head position
can be performed by setting bit 2 in the command
word to a logic 1. The verification operation begins at
the end of the 10 millisecond settling time after the
head is loaded against the media. The track number
from the first encountered 10 Field is compared
against the contents of the Track Register. If the
track numbers compare and the 10 Field Cyclic
Redundancy Check (CRC) is correct, the verify
operation is complete. If track comparison is not
5

5 Page





FD1771-01 arduino
INTRa. RESET BUSY
SET RECORD-NOT FOUND
NO
INTRO. RESET BUSY
SET RECORD-NOT FOUND
TYPE II COMMAND FLOW
INTRO. RESET BUSY
SET CRC ERROR
TYPE II COMMAND FLOW
Lost Data status bit is set. This sequence continues
until the complete data field has been input to the
computer. If there is a GRG error at the end of the
data field, the GRG error status bit is set, and the
command is terminated (even if it is a mulltiple
record command).
At the end of the Read operation, the type of Data
Address Mark encountered in the data field is recor-
ded in the Status Register (Bits 5 and 6) as shown
below.
Status
Bit 5
0
0
1
1
Status
Bit 6
0
1
0
1
Data AM
(Hex)
FB
FA
F9
F8
WRITE COMMAND
Upon receipt of the Write command, the head is
loaded (HLD active) and the BUSY status bit is set.
When an 10 field is encountered that has the correct
track number, correct sector number, and correct
eRG, a ORO is generated. The FD1771 counts off 11
bytes from the GRG field and the Write Gate (WG)
output is made active if the ORO is serviced (i.e., the
DR has been loaded by the computer). If ORO has
not been serviced, the command is terminated and
the Lost Data status bit is set. If the ORO has been ser-
viced, the WG is made active and six bytes of zeros
are then written on the disk. At this time the Data
Address Mark is then written on the disk as deter-
mined by the a, ao field of the command as shown
on next page.
The FD1771 then writes the data field and generates
DROs to the computer. If the ORO is not serviced in
11

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