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PDF GTLP36T612 Data sheet ( Hoja de datos )

Número de pieza GTLP36T612
Descripción 36-Bit LVTTL/GTLP Universal Bus Transceiver
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! GTLP36T612 Hoja de datos, Descripción, Manual

September 2001
Revised July 2002
GTLP36T612
36-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
The GTLP36T612 is an 36-bit universal bus transceiver
which provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface for
cards operating at LVTTL logic levels and a backplane
operating at GTLP logic levels. High speed backplane
operation is a direct result of GTLP’s reduced output swing
(< 1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different output
levels and receiver thresholds. GTLP output LOW level is
less than 0.5V, the output HIGH is 1.5V and the receiver
threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic
levels
s Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
s Partitioned as two 18-Bit transceivers with individual
latch timing and output control
s VREF pin provides external supply reference voltage for
receiver threshold adjustibility
s Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s TTL compatible driver and control inputs
s Designed using Fairchild advanced BiCMOS technology
s Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s Power up/down and power off high impedance for live
insertion
s Open drain on GTLP to support wired-or connection
s Flow through pinout optimizes PCB layout
s D-type flip-flop, latch and transparent data paths
s A Port source/sink 24mA/+24mA
s B Port sink +50mA
s For more information see AN-5026,
Using BGA Packages
Ordering Code:
Order Number Package Number
Package Description
GTLP36T612G
(Note 1)(Note 2)
BGA114A
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1: Ordering code Gindicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
© 2002 Fairchild Semiconductor Corporation DS500590
www.fairchildsemi.com

1 page




GTLP36T612 pdf
DC Electrical Characteristics (Continued)
Symbol
Test Conditions
Min Typ Max
(Note 9)
Units
ICC
(Note 12)
A Port and
Control Pins
VCC = 3.45V,
One Input at 2.7V
A or Control Inputs at VCC or GND
Ci Control Pins
VI = VCC or 0
A Port
VI = VCC or 0
B Port
VI = VCC or 0
Note 9: All typical values are at VCC = 3.3V, VCCQ = 3.3V, and TA = 25°C.
2 mA
6
7.5 pF
9.0
Note 10: GTLP VREF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy.
In addition, VTT and Rterm can be adjusted beyond the recommended operating conditions to accommodate backplane impedances other than 50, but
must remain within the boundaries of the DC Absolute Maximum ratings. Similarly VREF can be adjusted to optimize noise margin.
Note 11: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
Note 12: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
AC Operating Requirements
Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted).
Symbol
Test Conditions
Min Max
fMAX
tWIDTH
Maximum Clock Frequency
Pulse Duration
LEAB or LEBA HIGH
CLKAB or CLKBA HIGH or LOW
175
3.0
3.0
tSU Setup Time
A before CLKAB
B before CLKBA
1.1
3.0
A before LEAB
1.1
B before LEBA
2.7
CEAB before CLKAB
1.2
tHOLD
Hold Time
CEBA before CLKBA
A after CLKAB
B after CLKBA
A after LEAB
B after LEBA
1.4
0.0
0.0
0.8
0.0
CEAB after CLKAB
1.0
CEBA after CLKBA
1.9
Unit
MHz
ns
ns
ns
5 www.fairchildsemi.com

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