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PDF GTLP18T612MTD Data sheet ( Hoja de datos )

Número de pieza GTLP18T612MTD
Descripción 18-Bit LVTTL/GTLP Universal Bus Transceiver
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! GTLP18T612MTD Hoja de datos, Descripción, Manual

May 1999
Revised September 1999
GTLP18T612
18-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
The GTLP18T612 is an 18-bit universal bus transceiver
which provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface for
cards operating at LVTTL logic levels and a backplane
operating at GTLP logic levels. High speed backplane
operation is a direct result of GTLP’s reduced output swing
(< 1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild's GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different output
levels and receiver thresholds. GTLP output LOW level is
less than 0.5V, the output HIGH is 1.5V and the receiver
threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic
levels
s Edge Rate Control to minimize noise on the GTLP port
s Power up/down high impedance for live insertion
s External VREF pin for receiver threshold
s BiCMOS technology for low power dissipation
s Bushold data inputs on A Port eliminates the need for
external pull-up resistors for unused inputs
s LVTTL compatible Driver and Control inputs
s Flow-through architecture optimizes PCB layout
s Open drain on GTLP to support wired-or connection
s A-Port source/sink 24 mA/+24 mA
s B-Port sink capability +50 mA
s D-type flip-flop, latch and transparent data paths
Ordering Code:
Order Number Package Number
Package Description
GTLP18T612MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
GTLP18T612MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation DS500169
www.fairchildsemi.com

1 page




GTLP18T612MTD pdf
DC Electrical Characteristics (Continued)
Symbol
Test Conditions
Typ
Min Max
(Note 7)
Units
ICC A or B Ports
VCC = 3.45V
Outputs HIGH
(VCC/VCCQ)
IO = 0
Outputs LOW
VI = VCC or GND
Outputs Disabled
ICC
A Port and
VCC = 3.45V,
One Input at 2.7V
(Note 10) Control Pins
A or Control Inputs at VCC or GND
Ci Control Pins
VI = VCC or 0
A Port
VI = VCC or 0
B Port
VI = VCC or 0
Note 7: All typical values are at VCC = 3.3V, VCCQ = 3.3V, and TA = 25°C.
30 40
30 40 mA
30 45
0 2 mA
6
7.5 pF
9.0
Note 8: GTLP VREF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In
addition, VTT and Rterm can be adjusted beyond the recommended operating conditions to accommodate backplane impedances other than 50, but must
remain within the boundaries of the DC Absolute Maximum ratings. Similarly VREF can be adjusted to optimize noise margin.
Note 9: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
Note 10: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
AC Operating Requirements
Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted).
Symbol
Test Conditions
Min Max
fCLOCK
tWIDTH
tSU
Maximum Clock Frequency
Pulse Duration
Setup Time
LEAB or LEBA HIGH
CLKAB or CLKBA HIGH or LOW
A before CLKAB
B before CLKBA
A before LEAB
B before LEBA
0 175
3.0
3.0
1.1
3.0
1.1
2.7
CEAB before CLKAB
1.2
tHOLD
Hold Time
CEBA before CLKBA
A after CLKAB
B after CLKBA
A after LEAB
B after LEBA
1.4
0.0
0.0
0.8
0.0
CEAB after CLKAB
1.0
CEBA after CLKBA
1.9
Unit
MHz
ns
ns
ns
5 www.fairchildsemi.com

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