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Número de pieza | GTLP16616MTD | |
Descripción | 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock | |
Fabricantes | Fairchild Semiconductor | |
Logotipo | ||
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No Preview Available ! June 1997
Revised October 1998
GTLP16616
17-Bit TTL/GTLP Bus Transceiver
with Buffered Clock
General Description
The GTLP16616 is a 17-bit registered bus transceiver that
provides TTL to GTLP signal level translation. It allows for
transparent, latched and clocked modes of data flow and
provides a buffered GTLP (CLKOUT) clock output from the
TTL CLKAB. The device provides a high speed interface
between cards operating at TTL logic levels and a back-
plane operating at GTLP logic levels. High speed back-
plane operation is a direct result of GTLP’s reduced output
swing (<1V), reduced input threshold levels and output
edge rate control. The edge rate control minimizes bus set-
tling time. GTLP is a Fairchild Semiconductor derivative of
the Gunning Transceiver logic (GTL) JEDEC standard
JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and TTL logic
levels
s Edge Rate Control to minimize noise on the GTLP port
s Power up/down/off high impedance for live insertion
s External VREF pin for receiver threshold
s CMOS technology for low power dissipation
s 5 V tolerant inputs and outputs on the A-Port
s Bus-hold data inputs on the A-Port eliminates the need
for external pull-up resistors on unused inputs.
s TTL compatible driver and control inputs
s Flow through pinout optimizes PCB layout
s Open drain on GTLP to support wired-or connection
s A-port source/sink −32 mA/+32 mA
s D-type flip-flop, latch and transparent data paths
s GTLP Buffered CLKAB signal available (CLKOUT)
s Recommended Operating Temperature −40°C to 85°C
Ordering Code:
Order Number Package Number
Package Description
GTLP16616MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300” Wide
GTLP16616MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 1998 Fairchild Semiconductor Corporation DS500017.prf
www.fairchildsemi.com
1 page DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted).
Symbol
Test Conditions
Min
Typ
(Note 7)
VIH B-Port
Others
VREF +0.1
2.0
VIL B-Port
Others
0.0
VREF
GTLP
GTL
1.0
0.8
VIK
VOH
VOL
II
IOFF
A-Port
A-Port
B-Port
Control Pins
A-Port
B-Port
A-Port and
Control Pins
VCC = 3.15V,
VCCQ = 4.75V
VCC, VCCQ = Min to Max (Note 8)
VCC = 3.15V
VCCQ = 4.75V
VCC, VCCQ = Min to Max (Note 8)
VCC = 3.15V
VCCQ = 4.75V
VCC = 3.15V VCCQ = 4.75V
VCC, VCCQ = 0 or Max
VCC = 3.45V
VCCQ = 5.25V
VCC = 3.45V
VCCQ = 5.25V
VCC = VCCQ = 0
II = −18 mA
IOH = −100 µA
IOH = −8 mA
IOH = −32 mA
IOL = 100 µA
IOL = 32 mA
IOL = 34 mA
VI = 5.5V or 0V
VI = 5.5V
VI = VCC
VI = 0
VI = VCC
VI = 0
VI or VO = 0 to 4.5V
VCC −0.2
2.4
2.0
II(hold)
A-Port
IOZH
IOZL
ICCQ
(VCCQ)
A-Port
B-Port
A-Port
B-Port
A or B
Ports
ICC
(VCC)
A or B
Ports
VCC = 3.15V,
VCCQ = 4.75V
VCC = 3.45V,
VCCQ = 5.25V
VCC = 3.45V,
VCCQ = 5.25V
VCC = 3.45V,
VI = 0.8V
VI = 2.0V
VO = 3.45V
VO = 1.5V
VO = 0
VO = 0.65V
Outputs HIGH
VCCQ = 5.25V,
IO = 0,
VI = VCCQ or GND
VCC = 3.45V, VCCQ = 5.25V, IO = 0,
Outputs LOW
Outputs Disabled
Outputs HIGH
Outputs LOW
75
−20
30
30
30
0
0
∆ICC
(Note 9)
A-Port and
Control Pins
VI = VCC or GND
VCC = 3.45V,
VCC = 5.25V,
A or Control Inputs at
Outputs Disabled
One Input at 2.7V
0
0
VCC or GND
CIN Control Pins
VI = VCCQ or 0
8
CI/O A-Port
VI = VCCQ or 0
9
CI/O B-Port
VI = VCCQ or 0
6
Note 7: All typical values are at VCC = 3.3V, VCCQ = 5.0V, and TA = 25°C.
Note 8: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
Note 9: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Max Units
VTT
VREF −0.1
0.8
−1.2
V
V
V
V
V
V
V
V
0.2 V
0.5
0.65 V
±10 µA
20
1 µA
−30
5 µA
−5
100 µA
µA
1 µA
5
−20 µA
−10
40
40 mA
40
1
1 mA
1
1 mA
pF
5 www.fairchildsemi.com
5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet GTLP16616MTD.PDF ] |
Número de pieza | Descripción | Fabricantes |
GTLP16616MTD | 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock | Fairchild Semiconductor |
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