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Número de pieza | GTLP16612MTD | |
Descripción | CMOS 18-Bit TTL/GTLP Universal Bus Transceiver | |
Fabricantes | Fairchild Semiconductor | |
Logotipo | ||
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No Preview Available ! March 1995
Revised October 1998
GTLP16612
CMOS 18-Bit TTL/GTLP Universal Bus Transceiver
General Description
The GTLP16612 is an 18-bit universal bus transceiver
which provides TTL to GTLP signal level translation. The
device is designed to provide a high speed interface
between cards operating at TTL logic levels and a back-
plane operating at GTLP logic levels. High speed back-
plane operation is a direct result of GTLP’s reduced output
swing (<1V), reduced input threshold levels and output
edge rate control which minimizes signal settling times.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transceiver Logic (GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different driver
output levels and receiver threshold. GTLP output low volt-
age is typically less than 0.5V, the output high is 1.5V and
the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and TTL logic
levels
s Designed with Edge Rate Control Circuit to reduce
output noise
s VREF pin provides external supply reference voltage for
receiver threshold
s Submicron Core CMOS technology for low power
dissipation
s Special PVT Compensation circuitry to provide consis-
tent performance over variations of process, supply
voltage and temperature
s 5V tolerant inputs and outputs on A-Port
s Bus-Hold data inputs on A-Port to eliminate the need for
external pull-up resistors for unused inputs
s Power up/down high impedance
s TTL compatible Driver and Control inputs
s A-Port outputs source/sink −32 mA/+32 mA
s Flow-through architecture optimizes PCB layout
s Open drain on GTLP to support wired-or connection
Ordering Code:
Order Number Package Number
Package Description
GTLP16612MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300” Wide
GTLP16612MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 1998 Fairchild Semiconductor Corporation DS012390.prf
www.fairchildsemi.com
1 page DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (Unless Otherwise Noted).
Symbol
Test Conditions
Min
Typ
(Note 7)
VIH B-Port
Others
VREF +0.1
2.0
VIL B-Port
Others
0.0
VREF
VIK
VOH
VOL
II
A-Port
A-Port
B-Port
Control Pins
A-Port
VCC = 3.15V,
VCCQ = 4.75V
VCC, VCCQ = Min to Max (Note 8)
VCC = 3.15V
VCCQ = 4.75V
VCC, VCCQ = Min to Max (Note 8)
VCC = 3.15V
VCCQ = 4.75V
VCC = 3.15V VCCQ = 4.75V
VCC, VCCQ = 0 or Max
VCC = 3.45V
VCCQ = 5.25V
B-Port
IOFF
II(hold)
A-Port
A-Port
IOZH
IOZL
ICCQ
(VCCQ)
A-Port
B-Port
A-Port
B-Port
A or B
Ports
ICC
(VCC)
A or B
Ports
∆ICC
(Note 9)
A-Port and
Control Pins
VCC = 3.45V
VCCQ = 5.25V
VCC = VCCQ = 0
VCC = 3.15V,
VCCQ = 4.75V
VCC = 3.45V,
VCCQ = 5.25V
VCC = 3.45V,
VCCQ = 5.25V
VCC = 3.45V,
VCCQ = 5.25V,
IO = 0,
VI = VCCQ or GND
VCC = 3.45V,
VCCQ = 5.25V,
IO = 0,
VI = VCCQ or GND
VCC = 3.45V,
VCCQ = 5.25V,
A or Control Inputs at
II = −18 mA
IOH = −100 µA
IOH = −8 mA
IOH = −32 mA
IOL = 100 µA
IOL = 32 mA
IOL = 34 mA
VI = 5.5V or 0V
VI = 5.5V
VI = VCC
VI = 0
VI = VCCQ
VI = 0
VI or VO = 0 to 4.5V
VI = 0.8V
VI = 2.0V
VO = 3.45V
VO = 1.5V
VO = 0
VO = 0.65V
Outputs HIGH
Outputs LOW
Outputs Disabled
Outputs HIGH
Outputs LOW
Outputs Disabled
One Input at 2.7V
1.0
VCC − 0.2
2.4
2.0
75
−20
30
30
30
0
0
0
0
VCC or GND
CIN Control Pins
VI = VCCQ or 0
8
CI/O A-Port
VI = VCCQ or 0
9
CI/O B-Port
VI = VCCQ or 0
6
Note 7: All typicaI values are at VCC = 3.3V, VCCQ = 5.0V, and TA = 25°C.
Note 8: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
Note 9: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Max
VTT
VREF −0.1
0.8
−1.2
0.2
0.5
0.65
±10
20
1
−30
5
−5
100
1
5
−20
−10
40
40
40
1
1
1
1
Units
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
pF
5 www.fairchildsemi.com
5 Page |
Páginas | Total 9 Páginas | |
PDF Descargar | [ Datasheet GTLP16612MTD.PDF ] |
Número de pieza | Descripción | Fabricantes |
GTLP16612MTD | CMOS 18-Bit TTL/GTLP Universal Bus Transceiver | Fairchild Semiconductor |
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