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PDF GTLP10B320MTD Data sheet ( Hoja de datos )

Número de pieza GTLP10B320MTD
Descripción 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! GTLP10B320MTD Hoja de datos, Descripción, Manual

May 2001
Revised May 2001
GTLP10B320
10-Bit LVTTL/GTLP Transceiver
with Split LVTTL Port and Feedback Path
General Description
The GTLP10B320 is a 10-bit Universal bus driver and
receiver, with separate LVTTL inputs and outputs and a
feedback path for diagnostics, that provides LVTTL to
GTLP signal level translation. High speed backplane oper-
ation is a direct result of GTLP’s reduced output swing
(<1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the
Gunning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output low level is typ-
ically less than 0.5V, the output level high is 1.5V and the
receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic
levels
s Variable edge rate control pin to select desired edge rate
on GTLP port (VERC)
s VREF pin provides external supply reference voltage for
receiver threshold adjustibility
s Split LVTTL inputs and outputs
s Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s A feedback path for control and diagnostics monitoring
s TTL compatible driver and control inputs
s Designed using Fairchild advanced BiCMOS technology
s Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s Power up/down and power off high impedance for live
insertion
s Open drain on GTLP to support wired-or connection
s Flow through pinout optimizes PCB layout
s A Port source/sink 24mA/+24mA
s B Port sink +50mA
Ordering Code:
Order Number Package Number
Package Description
GTLP10B320MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device is also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
© 2001 Fairchild Semiconductor Corporation DS500483
www.fairchildsemi.com

1 page




GTLP10B320MTD pdf
Absolute Maximum Ratings(Note 5)
Supply Voltage (VCC)
DC Input Voltage (VI)
DC Output Voltage (VO)
Outputs 3-STATE
Outputs Active (Note 6)
DC Output Sink Current into
C Port IOL
DC Output Source Current from
C Port IOH
DC Output Sink Current into
B Port in the LOW State, IOL
DC Input Diode Current (IIK)
VI < 0V
DC Output Diode Current (IOK)
VO < 0V
ESD Rating
Storage Temperature (TSTG)
0.5V to +4.6V
0.5V to +4.6V
0.5V to +4.6V
0.5V to +4.6V
48 mA
48 mA
100 mA
50 mA
50 mA
>2000V
65°C to +150°C
Recommended Operating
Conditions
Supply Voltage VCC
Bus Termination Voltage (VTT)
GTLP
3.15V to 3.45V
1.47V to 1.53V
VREF
Input Voltage (VI)
on A Port and Control Pins
HIGH Level Output Current (IOH)
C Port
0.98V to 1.02V
0.0V to VCC
24 mA
LOW Level Output Current (IOL)
C Port
+24 mA
B Port
+50 mA
Operating Temperature (TA)
40°C to +85°C
Note 5: Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed. The device should not be oper-
ated at these limits. The parametric values defined in the Electrical Char-
acteristicstable are not guaranteed at the absolute maximum rating. The
Recommended Operating Conditionstable will define the conditions for
actual device operation.
Note 6: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted).
Symbol
Test Conditions
Min
VIH
VIL
VREF
VTT
VIK
VOH
VOL
II
IOFF
B Port
Others
B Port
Others
B Port
B Port
C Port
VCC = 3.15V
VCC = Min to Max (Note 8)
VCC = 3.15V
C Port
VCC = Min to Max (Note 8)
VCC = 3.15V
B Port
VCC = 3.15V
Control Pins
and A Port
B Port
VCC = 3.45V
VCC = 3.45V
A or C Ports, VCC = 0
Control Pins
B Port
VCC = 0
VREF + 0.05
2.0
0.0
0.7
VREF + 50 mV
II = −18 mA
IOH = −100 µA
VCC 0.2
IOH = −8 mA
2.4
IOH = -24mA
2.2
IOL = 100 µA
IOL = 8 mA
IOL = 24 mA
IOL = 40 mA
IOL = 50 mA
VI = 3.45V
VI = 0V
VI = VTT
VI = 0
VI or VO = 0 to 3.45V
VI or VO = 0 to 1.5V
Typ
(Note 7)
1.0
1.5
Max
VTT
VREF 0.05
0.8
1.3
VCC
1.2
0.2
0.4
0.5
0.4
0.5
10
10
5
5
30
30
Units
V
V
V
V
V
V
V
V
µA
µA
µA
µA
II (HOLD)
IOZH
IOZL
IPU/PD
A Port
C Port
B Port
C Port
B Port
All Ports
VCC = 3.15V
VCC = 3.45V
VCC = 3.45V
VCC = 0 to 1.5V
VI = 0.8V
VI = 2.0V
VO = 3.45V
VO = 1.5V
VO = 0V
VO = 0.55V
VI = 0 to 3.45V
75
µA
75
10
µA
5
10
µA
5
30 µA
5 www.fairchildsemi.com

5 Page





GTLP10B320MTD arduino
Test Circuits and Timing Waveforms
Test Circuit for A Outputs
Test Circuit for B Outputs
Test S
tPLH/tPHL Open
tPLZ/tPZL 6V
tPHZ/tPZH GND
Note A: CL includes probes and Jig capacitance.
Voltage Waveform - Propagation Delay Times
Note B: For B Port, CL = 30 pF or 10 pF.
Voltage Waveform - Setup and Hold Times
Voltage Waveform - Pulse Width
Voltage Waveform - Enable and Disable times
Output Waveform 1 is for an output with internal conditions such that the
output is LOW except when disabled by the control output.
Output Waveform 2 is for an output with internal conditions such that the
output is HIGH except when disabled by the control output.
Input and Measure Conditions
A or LVTTL B or GTLP
Pins
Pins
VinHIGH
VCC
1.5
VinLOW
0.0
0.0
VM VCC/2 1.0
VX
VOL + 0.3V
N/A
VY
VOH 0.3V
N/A
All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns (10% to 90%), ZO = 50
The outputs are measured one at a time with one transition per measurement.
11 www.fairchildsemi.com

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