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PDF AR2317 Data sheet ( Hoja de datos )
| Número de pieza | AR2317 | |
| Descripción | Single Chip MAC/Baseband/Radio and Processor | |
| Fabricantes | Atheros | |
| Logotipo |  |
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Data Sheet
PRELIMINARY
April 2006
AR2317 Single Chip MAC/Baseband/Radio and Processor
for 2.4 GHz Wireless LANs
General Description
Features
The Atheros AR2317 is an all-CMOS, fully-
■ Integrated high-output PA
integrated, single-chip 802.11b/g WLAN
■ Integrated LNA/optional external LNA
solution. It integrates the PA, LNA, 2.4GHz
support
radio, baseband PHY, MAC, and a MIPS 4000
■ Integrated 1.8 V voltage regulator; NO need
CPU into a single chip for wireless access point
for a 1.8 V supply
and router applications. Other major modules
■ Switched Rx antenna diversity
include 802.3 Ethernet MAC and MII interface,
■ Integrated Rx/Tx antenna switch
SDRAM controller, external memory interface
■ Integrated power detector
for Flash, ROM, or RAM, a UART, GPIOs as
■ 25 MHz output for Ethernet switch
well as LED controls.
The AR2317 implements an 802.11 MAC/BB
processor supporting all IEEE 802.11g data
rates (1 to 54 Mbps) and all IEEE 802.11b
Ycomplementary key coding (CCK) data rates
(1 to 11 Mbps). Additional features include
Pforward error correction coding at rates for 1/
2, 2/3, and 3/4, signal detection, automatic
Ogain control, frequency offset estimation,
symbol timing, channel estimation, error
Crecovery, enhanced security, and quality of
service (QoS). The AR2317 performs receive
Tand transmit filtering for IEEE 802.3 and 802.11
networks.
DO NOSystem Block Diagram
■ Integrated MIPS 4000 processor
■ 180 MHz processor frequency
■ IEEE 802.11b/g Access Point, Ad Hoc, and
station functions supported
■ OFDM and CCK modulation schemes
supported
■ Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36,
48, 54 Mbps
■ IEEE 802.3 Ethernet MAC supporting 10/
100 Mbps, full and half duplex, and MII
interface to external Ethernet PHY
■ UART for console support
■ IEEE 1149.1 standard test access port and
boundary scan architecture supported
■ EJTAG based debugging of the processor
core supported
■ Standard 0.18 μm CMOS technology
■ 12 mm x 12 mm 260 BGA package
Flash SDRAM Interface
LNA
LNA
RF
Switch
PA
AR2317
Receiver
Frequency
Synthesizer
Transmitter
Bias/
Control
SDRAM
Controller
and Memory
Interface
MIPS
Processor
Baseband
(PHY) and
Wireless MAC
Ethernet
MAC
Fast UART
Peripheral
Interface
MII Interface
40 MHz
Crystal
Serial Interface
LED Controls
GPIOs
© 2000-2006 by Atheros Communications, Inc. All rights reserved. Atheros™, 5-UP™, Driving the Wireless Future™, Atheros Driven™, Atheros Turbo
Mode™, and the Air is Cleaner at 5-GHz™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of
Atheros Communications, Inc. All other trademarks are the property of their respective holders.
Subject to change without notice.
COMPANY CONFIDENTIAL
•1
1 page  
PRELIMINARY
1. Pin Descriptions
This section contains both a package pinout
(see Table 1-1 through Table 1-3) and tabular
listings of the signal descriptions.
The following nomenclature is used for signal
names:
■ NC indicates no connection should be made
to this pin.
■ _L at the end of the signal name indicates
active low signal.
■ P at the end of the signal name indicates the
positive side of a differential signal.
■ N at the end of the signal name indicates the
negative side of a differential signal.
The following nomenclature is used for signal
types:
■ IA indicates an analog input signal.
■ I indicates a digital input signal.
■ IH indicates input signals with weak
internal pull-up, to prevent signals from
floating when left open.
■ IL indicates input signals with weak
internal pull-down, to prevent signals from
floating when left open.
■ I/O indicates a digital bidirectional signal.
■ OA indicates an analog output signal.
■ O indicates a digital output signal.
■ P indicates a power or ground signal.
DO NOT COPY
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR2317 MAC/BB/Radio and Processor for 2.4 GHz WLANs • 5
April 2006 • 5
5 Page 
PRELIMINARY
2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Table 2-1 summarizes the absolute maximum
ratings and Table 2-2 lists the recommended
operating conditions for the AR2317. Absolute
Table 2-1. Absolute Maximum Ratings
Symbol
VDD33
Tstore
ESD
Parameter
I/O Supply Voltage (3.3 V)
Storage Temperature
Electrostatic Discharge Tolerance
maximum ratings are those values beyond
which damage to the device can occur.
Functional operation under these conditions,
or at any other condition beyond those
indicated in the operational sections of this
document, is not recommended.
Max. Rating
–0.3 to 4.6
–65 to 150
2000
Unit
V
°C
V
2.1.1 Recommended Operating Conditions
Table 2-2. Recommended Operating Conditions
Symbol Parameter
Conditions
Min Typ Max Unit
VDD33
Tcase
YTJ
θJA
I/O Supply Voltage
Case Temperature
Junction Temperature
Junction to Ambient Temperature
± 10%
3.0 3.3 3.6
V
0 45 105 °C
0 50 115 °C
33 °C/W
P2.2 General DC Electrical Characteristics
OTable 2-3 lists the general DC electrical
Ccharacteristics. The following conditions apply
Table 2-3. General DC Electrical Characteristics
to all DC characteristics unless otherwise
specified:
Vdd = 3.3 V, Tamb = 25 °C
TSymbol
OVIH
NVIL
DOIIL
Parameter
High Level Input Voltage
Low Level Input Voltage
Input Leakage Current
Conditions
=Vout VOH (min)
Vout = VOL (min)
Without Pull-up or
Pull-down
With Pull-up or
Pull-down
Min
2.0
–0.3
—
—
Typ Max Unit
— Vdd + 0.3 V
— 0.8 V
± 5 — μA
± 65 — μA
VOH
High Level Output Voltage
No Load (Io = 0) Vdd –0.3 —
—V
Io = 12 mA
Vdd –0.8 —
—V
VOL Low Level Output Voltage
No Load (Io = 0)
—
—
0.20 V
Io = 12 mA
— — 0.27 V
IO Output Current
Vo = 0 to Vdd — — 6[1] mA
CIN Input Capacitance
—
—6
— pF
[1]Note these exceptions: the pins SD_ADDR[12:0] are 2 mA, SD_DATA[15:0] are 2mA, and TDO is 8 mA.
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR2317 MAC/BB/Radio and Processor for 2.4 GHz WLANs • 11
April 2006 • 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AR2317.PDF ] | |
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