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PDF UDA1360TS Data sheet ( Hoja de datos )
| Número de pieza | UDA1360TS | |
| Descripción | Low-voltage low-power stereo audio ADC | |
| Fabricantes | Philips | |
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INTEGRATED CIRCUITS
DATA SHEET
UDA1360TS
Low-voltage low-power stereo
audio ADC
Preliminary specification
Supersedes data of 1998 Oct 02
File under Integrated Circuits, IC01
2000 Feb 08
1 page  
Philips Semiconductors
Low-voltage low-power stereo audio ADC
Preliminary specification
UDA1360TS
Table 1 Application modes using input gain stage
RESISTOR
(12 kΩ)
Present
Present
Absent
Absent
INPUT GAIN
SWITCH
0 dB
6 dB
0 dB
6 dB
MAXIMUM INPUT
VOLTAGE
2 V (RMS)
1 V (RMS)
1 V (RMS)
0.5 V (RMS)
Multiple format output interface
The UDA1360TS supports the following data output
formats;
• I2S-bus with data word length of up to 20 bits
• MSB-justified serial format with data word length of up to
20 bits.
The output format can be set by the static SFOR pin. When
SFOR is LOW, the I2S-bus is selected, when SFOR is set
HIGH the MSB-justified format is selected.
The data formats are illustrated in Fig.4. Left and right data
channel words are time multiplexed.
Decimation filter
The decimation from 128fs is performed in two stages.
The first stage realizes 3rd-order sin x/x characteristic.
This filter decreases the sample rate by 16. The second
stage (an FIR filter) consists of 3 half-band filters, each
decimating by a factor of 2.
Mute
On recovery from power-down, the serial data output
DATAO is held LOW until valid data is available from the
decimation filter. This time tracks with the sampling
frequency:
t = 1----2---f2--s--8---8-- = 279 ms ; where fs = 44.1 kHz.
Power-down mode
The PWON pin can control the power saving together with
the optional gain switch for 2 V (RMS) or 1 V (RMS) input.
When the PWON pin is set LOW, the ADC is set to
power-down. When PWON is set to HIGH or to half the
power supply, then either 6 dB gain or 0 dB gain in the
analog front-end is selected.
Application modes
The UDA1360TS can be set to different modes using two
3-level pins and one 2-level pin. The selection of modes is
given in Table 3.
Table 3 Mode selection summary
PIN
SFOR
PWON
FSEL
VSS
1⁄2VDD
I2S-bus
test mode
power-down 0 dB gain
256fs
−
VDD
MSB
6 dB gain
384fs
Table 2 DC cancellation filter characteristics
ITEM
CONDITION
Pass-band ripple
Pass-band gain
Stop band
Droop
Attenuation at DC
Dynamic range
>0.55fs
at 0.00045fs
at 0.00000036fs
0 to 0.45fs
VALUE
(dB)
none
0
−60
0.031
>40
>110
2000 Feb 08
5
5 Page 
Philips Semiconductors
Low-voltage low-power stereo audio ADC
PACKAGE OUTLINE
SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
Preliminary specification
UDA1360TS
SOT369-1
D
y
Z
16
9
c
EA
X
HE v M A
pin 1 index
1
e
8
bp
wM
A2
A1
Q
(A3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
mm
1.5
0.15
0.00
1.4
1.2
0.25
0.32
0.20
0.25
0.13
D(1)
5.30
5.10
E(1) e
4.5
4.3
0.65
HE
6.6
6.2
L Lp Q v w y Z (1) θ
1.0
0.75 0.65
0.45 0.45
0.2
0.13
0.1
0.48
0.18
10o
0o
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
OUTLINE
VERSION
SOT369-1
IEC
REFERENCES
JEDEC
EIAJ
MO-152
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
99-12-27
2000 Feb 08
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet UDA1360TS.PDF ] | |
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