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PDF ZR36966ELCG-D Data sheet ( Hoja de datos )

Número de pieza ZR36966ELCG-D
Descripción DVD SoC
Fabricantes Zoran 
Logotipo Zoran Logotipo



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Data Sheet
ZR36966ELCG-D
DVD SoC
Preliminary version
Version 0.9
26 Dec 2005
ZORAN Proprietary
ZORAN Corporation, 1390 Kif1er Road, Sunnyvale, CA 94086-5305
Phone (408) 523-6500 Fax (408) 523-6501
ZORAN Proprietary

1 page




ZR36966ELCG-D pdf
Vaddis 966-D
1 Introduction
The Vaddis 966-D is Zoran’s ninth-generation of IC product for entry-level consumer DVD players. This highly-integrated device
includes the full front-end disc controller including the RF amplifier stage, back-end decoder functions including MPEG-4, DivX
memory cards and integrated audio DACs.
2 Functional Overview
TRAY
IR-RC
SPINDLE
>
>
SLED
>
OPU
>
<
>
Disc loader
Servo
AFE
ADP
Front Panel
Concentrator
SPI/I2C/GPIO
CPU
PLL
Vaddis
966-D
MCU
VPU
4-16 Mbits
NOR
Flash
27 MHz
RESET
16/64 Mbits
SDRAM
Audio
Servo
S/PDIF
2ch
Headphones
5.1 ch
Speakers
TV
Monitor
ZORAN Corporation, 1390 Kifer Road, Sunnyvale, CA 94086-5305
Phone (408) 523-6500 Fax (408) 523-6501
ZORAN Proprietary
4

5 Page





ZR36966ELCG-D arduino
Vaddis 966-D Data Sheet
3. Unit Description Page 9
3.2 CPU - Central Processing Unit
The CPU is the central processing unit of the Vaddis 966-D. It is based on a 16 bits Intel 186 instruction set
compatible licensed CPU core. The CPU executes from a NOR type Flash memory with 16 bit data bus.
Alternately, a compatible EPROM, PROM, OTPROM or masked ROM can be connected.
The CPU core has attached to it 2 KWords instruction/data cache to the flash, 1KWords data/instruction
cache to the SDRAM, 6KWords instruction ROM (most of it is dedicated to the DSP) shared with the DSP,
4KWords "scratch pad" data/instruction RAM and peripheral units mentioned below.
The core has internal real-time clock unit, two UART units, GPIO control unit and interrupt handler.
Most of the data transferred over the CPU_Bus are called CPU parameters. The CPU SW always writes and
reads 16 bits (or multiple of 16 bits transferred consecutively to/from the same CPU_Bus address) for each
parameter. CPU parameters written or read from the same address may or may not have the same name. In
the CPU parameters description in the following sections, only "active" bits are mentioned. All "non-active"
bits should be written with B‘0’ or return B‘0’ when read. It would be prudent for the CPU SW to ignore the
values read for of non-active bits. Non-active addresses should not be written to or read from at all.
CPU SW is responsible for user interface and player control, internal units set-up and control, navigation and
high level front end functions.
The CPU interfaces with the following external entities using GPIO functions: IR remote control receiver;
Audio ADCs and DACs; Serial flash memory; Other player chips and debug aids.
June 2005
9

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