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PDF GS9022-CTJ Data sheet ( Hoja de datos )

Número de pieza GS9022-CTJ
Descripción Digital Video Serializer
Fabricantes ETC 
Logotipo ETC Logotipo



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No Preview Available ! GS9022-CTJ Hoja de datos, Descripción, Manual

FEATURES
• built-in 75 cable driver with two serial outputs
• standard independent operation
• space saving 28 pin PLCC package
• 650 mW typical power dissipation (data output
driving 75 load).
• supports bit rates to 400 Mb/s
• accepts 8 bit and 10 bit TTL and CMOS
compatible parallel data inputs
• fully compatible with SMPTE 259M serial digital
standard
• single +5 or -5 volt supply
APPLICATIONS
• 4ƒSC, 4:2:2 and 360 Mb/s serial digital interfaces for:
Video cameras
VTRs
Signal generators
Portable equipment
GENLINXTM GS9022
Digital Video Serializer
DATA SHEET
DEVICE DESCRIPTION
The GS9022 is a monolithic bipolar integrated circuit designed
to serialize SMPTE 125M and SMPTE 244M bit parallel digital
signals as well as other 8 or 10 bit parallel formats. This device
performs the functions of sync detection, parallel to serial
conversion, data scrambling (using the X9 + X4 +1 algorithm),
10x parallel clock multiplication and conversion of NRZ to
NRZI serial data. The data rate is automatically set for SMPTE
259M data rates to 400 Mb/s. Other features include a lock
detect output and an internal cable driver capable of driving
two 75loads.
The device requires a single +5 volt or -5 volt supply and
typically consumes 650 mW of power while driving two 75
loads. The 28 pin PLCC packaging assures a small footprint
for the complete encoder function.
ORDERING INFORMATION
Part Number
Package
GS9022-CPJ
GS9022-CTJ
28 pin PLCC
28 pin PLCC Tape
Temperature
O°C to 70°C
O°C to 70°C
SYNC
DETECT
DISABLE
25
PARALLEL 3-12
DATA
IN (10 BITS)
INPUT
LATCH
SYNC
DETECT
P/S
CONVERTER
SCRAMBLER
NRZ
NRZI
RISE TIME
CONTROL
PLD
SCLK
MUX
22 SERIAL DATA
23 SERIAL DATA
PCLK 13
LOOP 17
FILTER
GS9022
PHASE
FREQUENCY
DETECT
CHARGE
PUMP
VCO
LOCK
DETECT
DIV BY 10
GENERATOR
DIV BY 2
GENERATOR
OSCILLATOR
14
LOCK
DETECT
19
RVCO
28
REGULATOR CAP
26
COSC
FUNCTIONAL BLOCK DIAGRAM
Revision Date: August 1997
Document No. 521 - 42 - 01
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946
Gennum Japan Corporation: A-302 Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168, Japan tel. (03) 3334-7700 fax (03) 3247-8839

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GS9022-CTJ pdf
INPUT / OUTPUT CIRCUITS
1k 1k
VCC
PINS 3-12
13, 25
VR1
VCC
10k
LOCK
DETECT
PIN 14
VEE
Fig. 1 Sync Detect Disable, Parallel Data,
Parallel Clock
VCC
VCC
400 400
VOUT
PIN 22
VCC
VOUT
PIN 23
VEE
Fig. 2 Lock Detect
PARALLEL
CLOCK
PLCK
PARALLEL
DATA
PDn
tCLKL = tCLKH
50%
tSU tHOLD
Fig. 4 Input Clock / Data Timing
Fig. 3 Output Circuit
5 521 - 42 - 01

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