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PDF GS88018AT-150I Data sheet ( Hoja de datos )

Número de pieza GS88018AT-150I
Descripción 512K x 18/ 256K x 32/ 256K x 36 9Mb Sync Burst SRAMs
Fabricantes ETC 
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No Preview Available ! GS88018AT-150I Hoja de datos, Descripción, Manual

100-Pin TQFP
Commercial Temp
Industrial Temp
GS88018/32/36AT-250/225/200/166/150/133
512K x 18, 256K x 32, 256K x 36 250 MHz133 MHz
9Mb Sync Burst SRAMs
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
Pipeline
3-1-1-1
tKQ
tCycle
-250 -225 -200 -166 -150 -133 Unit
2.5 2.7 3.0 3.4 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.7 7.5 ns
3.3 V
Curr (x18) 280 255 230 200 185 165 mA
Curr (x32/x36) 330 300 270 230 215 190 mA
2.5 V
Curr (x18) 275 250 230 195 180 165 mA
Curr (x32/x36) 320 295 265 225 210 185 mA
Flow
Through
2-1-1-1
tKQ
tCycle
5.5 6.0 6.5 7.0 7.5 8.5 ns
5.5 6.0 6.5 7.0 7.5 8.5 ns
3.3 V
2.5 V
Curr (x18) 175 165 160 150 145 135 mA
Curr (x32/x36) 200 190 180 170 165 150 mA
Curr (x18) 175 165 160 150 145 135 mA
Curr (x32/x36) 200 190 180 170 165 150 mA
Functional Description
Applications
The GS88018/32/36AT is a 9,437,184-bit (8,388,608-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode pin
low places the RAM in Flow Through mode, causing output
data to bypass the Data Output Register. Holding FT high
places the RAM in Pipeline mode, activating the rising-edge-
triggered Data Output Register.
SCD Pipelined Reads
The GS88018/32/36AT is a SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88018/32/36AT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Rev: 1.02 9/2002
1/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.

1 page




GS88018AT-150I pdf
TQFP Pin Description
Symbol
Type
A0, A1
A2A17
A18
DQA1DQA9
DQB1DQB9
DQC1DQC9
DQD1DQD9
NC
I
I
I
I/O
BW I
BA, BB, BC, BD
CK
I
I
GW I
E1, E3
E2
G
I
I
I
ADV I
ADSP, ADSC
I
ZZ I
FT I
LBO I
VDD
VSS
VDDQ
I
I
I
GS88018/32/36AT-250/225/200/166/150/133
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Address Input
Data Input and Output pin
No Connect
Byte WriteWrites all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Clock Input Signal; active high
Global Write EnableWrites all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.02 9/2002
5/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.

5 Page





GS88018AT-150I arduino
GS88018/32/36AT-250/225/200/166/150/133
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD
VDDQ
VCK
VI/O
VIN
IIN
IOUT
PD
TSTG
TBIAS
Voltage on VDD Pins
Voltage in VDDQ Pins
Voltage on Clock Input Pin
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
Temperature Under Bias
0.5 to 4.6
0.5 to 4.6
0.5 to 6
0.5 to VDDQ +0.5 (4.6 V max.)
0.5 to VDD +0.5 (4.6 V max.)
+/20
+/20
1.5
55 to 125
55 to 125
V
V
V
V
V
mA
mA
W
oC
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Rev: 1.02 9/2002
11/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.

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