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PDF GS84036AT-100I Data sheet ( Hoja de datos )

Número de pieza GS84036AT-100I
Descripción 256K x 18/ 128K x 32/ 128K x 36 4Mb Sync Burst SRAMs
Fabricantes ETC 
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No Preview Available ! GS84036AT-100I Hoja de datos, Descripción, Manual

TQFP, BGA
Commercial Temp
Industrial Temp
Preliminary
GS84018/32/36AT/B-180/166/150/100
256K x 18, 128K x 32, 128K x 36 180 MHz–100 MHz
4Mb Sync Burst SRAMs
3.3 V VDD
3.3 V and 2.5 V I/O
Features
• FT pin for user-configurable flow through or pipelined
operation
• Single Cycle Deselect (SCD) operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipelined mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC standard 100-lead TQFP or 119-Bump BGA package
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
tCycle
tKQ
IDD
tKQ
tCycle
IDD
–180
5.5 ns
3.0 ns
185 mA
8 ns
9.1 ns
115 mA
–166
6.0 ns
3.5 ns
170 mA
8.5 ns
10 ns
105 mA
–150
6.6 ns
3.8 ns
155 mA
10 ns
12 ns
100 mA
–100
10 ns
4.5 ns
105 mA
12 ns
15 ns
80 mA
Functional Description
Applications
The GS84018/32/36A is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a 2-
bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications ranging from DSP main store
to networking chip set support. The GS84018/32/36A is
available in a JEDEC standard 100-lead TQFP or 119-Bump
BGA package.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin/bump (pin 14 in the TQFP and
bump 5R in the BGA). Holding the FT mode pin/bump low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipelined mode, activating the rising-edge-triggered
Data Output Register.
SCD Pipelined Reads
The GS84018/32/36A is an SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS84018/32/36A operates on a 3.3 V power supply and
all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (VDDQ) pins are used to de-couple output noise
from the internal circuit.
Rev: 1.12 7/2002
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.

1 page




GS84036AT-100I pdf
TQFP Pin Description
Pin Location
37, 36
35, 34, 33, 32, 100, 99, 82, 81,44, 45, 46,
47, 48, 49, 50
80
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
18, 19, 22, 23, 24, 25, 28, 29
51, 80, 1, 30
51, 80, 1, 30
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57
75, 78, 79
1, 2, 3, 6, 7
25, 28, 29, 30
87
93, 94
Symbol
A0, A1
A2–A16
A17
DQA1–DQA8
DQB1–DQB8
DQC1–DQC8
DQD1–DQD8
DQA9, DQB9,
DQC9, DQD9
NC
DQA1–DQA9
DQB1–DQB9
NC
BW
BA, BB
Type
I
I
I
I/O
I/O
I/O
-
I
I
95, 96
BC, BD
I
95, 96
89
88
98, 92
97
86
83
84, 85
64
14
31
15, 41, 65, 91
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
16, 38, 39, 42, 43, 66
NC
CK
GW
E1, E3
E2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
VDD
VSS
VDDQ
NC
-
I
I
I
I
I
I
I
I
I
I
I
I
I
-
Preliminary
GS84018/32/36AT/B-180/166/150/100
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Address Inputs (x18 versions)
Data Input and Output pins. (x32, x36 Version)
Data Input and Output pins (x36 Version)
No Connect (x32 Version)
Data Input and Output pins (x18 Version)
No Connect (x18 Version)
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/’s; active low
Byte Write Enable for DQC, DQD Data I/Os; active low
(x32, x36 Version)
No Connect (x18 Version)
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
No Connect
Rev: 1.12 7/2002
5/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.

5 Page





GS84036AT-100I arduino
Preliminary
GS84018/32/36AT/B-180/166/150/100
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
H or NC
Linear Burst
Interleaved Burst
Output Register Control
FT
L
H or NC
Flow Through
Pipeline
Power Down Control
L or NC
ZZ H
Active
Standby, IDD = ISB
Note:
There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00 01 10 11
1st address
00 01 10 11
2nd address
01 10 11 00
2nd address
01 00 11 10
3rd address
10 11 00 01
3rd address
10 11 00 01
4th address
11 00 01 10
Note: The burst counter wraps to initial state on the 5th clock.
4th address
11 10 01 00
Note: The burst counter wraps to initial state on the 5th clock.
Byte Write Truth Table
Function
GW BW
BA
BB
BC
BD Notes
Read H H X X X X 1
Read H L H H H H 1
Write byte A
H
L
L
H
H
H 2, 3
Write byte B
H
L
H
L
H
H 2, 3
Write byte C
H
L
H
H
L
H 2, 3, 4
Write byte D
H
L
H
H
H
L 2, 3, 4
Write all bytes
H
L
L
L
L
L 2, 3, 4
Write all bytes
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.12 7/2002
11/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.

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